53 lines
1.3 KiB
YAML
53 lines
1.3 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: RISC-V timer
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maintainers:
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- Anup Patel <anup@brainfault.org>
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description: |+
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RISC-V platforms always have a RISC-V timer device for the supervisor-mode
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based on the time CSR defined by the RISC-V privileged specification. The
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timer interrupts of this device are configured using the RISC-V SBI Time
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extension or the RISC-V Sstc extension.
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The clock frequency of RISC-V timer device is specified via the
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"timebase-frequency" DT property of "/cpus" DT node which is described
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in Documentation/devicetree/bindings/riscv/cpus.yaml
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properties:
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compatible:
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enum:
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- riscv,timer
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interrupts-extended:
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minItems: 1
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maxItems: 4096 # Should be enough?
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riscv,timer-cannot-wake-cpu:
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type: boolean
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description:
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If present, the timer interrupt cannot wake up the CPU from one or
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more suspend/idle states.
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additionalProperties: false
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required:
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- compatible
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- interrupts-extended
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examples:
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- |
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timer {
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compatible = "riscv,timer";
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interrupts-extended = <&cpu1intc 5>,
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<&cpu2intc 5>,
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<&cpu3intc 5>,
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<&cpu4intc 5>;
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};
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...
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