103 lines
2.4 KiB
YAML
103 lines
2.4 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/cdns,usb3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence USBSS-DRD controller
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maintainers:
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- Pawel Laszczak <pawell@cadence.com>
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properties:
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compatible:
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const: cdns,usb3
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reg:
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items:
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- description: OTG controller registers
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- description: XHCI Host controller registers
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- description: DEVICE controller registers
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reg-names:
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items:
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- const: otg
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- const: xhci
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- const: dev
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interrupts:
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minItems: 3
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items:
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- description: XHCI host controller interrupt
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- description: Device controller interrupt
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- description: OTG/DRD controller interrupt
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- description: interrupt used to wake up core, e.g when usbcmd.rs is
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cleared by xhci core, this interrupt is optional
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interrupt-names:
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minItems: 3
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items:
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- const: host
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- const: peripheral
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- const: otg
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- const: wakeup
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dr_mode:
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enum: [host, otg, peripheral]
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maximum-speed:
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enum: [super-speed, high-speed, full-speed]
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phys:
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minItems: 1
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maxItems: 2
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phy-names:
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minItems: 1
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maxItems: 2
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items:
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anyOf:
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- const: cdns3,usb2-phy
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- const: cdns3,usb3-phy
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cdns,on-chip-buff-size:
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description:
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size of memory intended as internal memory for endpoints
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buffers expressed in KB
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$ref: /schemas/types.yaml#/definitions/uint16
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cdns,phyrst-a-enable:
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description: Enable resetting of PHY if Rx fail is detected
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type: boolean
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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usb@6000000 {
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compatible = "cdns,usb3";
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reg = <0x00 0x6000000 0x00 0x10000>,
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<0x00 0x6010000 0x00 0x10000>,
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<0x00 0x6020000 0x00 0x10000>;
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reg-names = "otg", "xhci", "dev";
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "host", "peripheral", "otg";
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maximum-speed = "super-speed";
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dr_mode = "otg";
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};
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};
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