384 lines
12 KiB
ReStructuredText
384 lines
12 KiB
ReStructuredText
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.. SPDX-License-Identifier: GPL-2.0
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.. include:: <isonum.txt>
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===================================
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Compute Express Link Memory Devices
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===================================
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A Compute Express Link Memory Device is a CXL component that implements the
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CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
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or both. It is enumerated as a PCI device for configuration and passing
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messages over an MMIO mailbox. Its contribution to the System Physical
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Address space is handled via HDM (Host Managed Device Memory) decoders
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that optionally define a device's contribution to an interleaved address
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range across multiple devices underneath a host-bridge or interleaved
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across host-bridges.
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CXL Bus: Theory of Operation
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============================
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Similar to how a RAID driver takes disk objects and assembles them into a new
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logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
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assemble them into a CXL.mem decode topology. The need for runtime configuration
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of the CXL.mem topology is also similar to RAID in that different environments
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with the same hardware configuration may decide to assemble the topology in
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contrasting ways. One may choose performance (RAID0) striping memory across
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multiple Host Bridges and endpoints while another may opt for fault tolerance
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and disable any striping in the CXL.mem topology.
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Platform firmware enumerates a menu of interleave options at the "CXL root port"
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(Linux term for the top of the CXL decode topology). From there, PCIe topology
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dictates which endpoints can participate in which Host Bridge decode regimes.
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Each PCIe Switch in the path between the root and an endpoint introduces a point
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at which the interleave can be split. For example platform firmware may say at a
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given range only decodes to 1 one Host Bridge, but that Host Bridge may in turn
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interleave cycles across multiple Root Ports. An intervening Switch between a
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port and an endpoint may interleave cycles across multiple Downstream Switch
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Ports, etc.
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Here is a sample listing of a CXL topology defined by 'cxl_test'. The 'cxl_test'
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module generates an emulated CXL topology of 2 Host Bridges each with 2 Root
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Ports. Each of those Root Ports are connected to 2-way switches with endpoints
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connected to those downstream ports for a total of 8 endpoints::
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# cxl list -BEMPu -b cxl_test
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{
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"bus":"root3",
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"provider":"cxl_test",
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"ports:root3":[
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{
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"port":"port5",
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"host":"cxl_host_bridge.1",
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"ports:port5":[
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{
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"port":"port8",
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"host":"cxl_switch_uport.1",
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"endpoints:port8":[
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{
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"endpoint":"endpoint9",
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"host":"mem2",
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"memdev":{
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"memdev":"mem2",
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"pmem_size":"256.00 MiB (268.44 MB)",
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"ram_size":"256.00 MiB (268.44 MB)",
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"serial":"0x1",
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"numa_node":1,
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"host":"cxl_mem.1"
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}
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},
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{
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"endpoint":"endpoint15",
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"host":"mem6",
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"memdev":{
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"memdev":"mem6",
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"pmem_size":"256.00 MiB (268.44 MB)",
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"ram_size":"256.00 MiB (268.44 MB)",
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"serial":"0x5",
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"numa_node":1,
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"host":"cxl_mem.5"
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}
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}
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]
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},
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{
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"port":"port12",
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"host":"cxl_switch_uport.3",
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"endpoints:port12":[
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{
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"endpoint":"endpoint17",
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"host":"mem8",
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"memdev":{
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"memdev":"mem8",
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"pmem_size":"256.00 MiB (268.44 MB)",
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"ram_size":"256.00 MiB (268.44 MB)",
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"serial":"0x7",
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"numa_node":1,
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"host":"cxl_mem.7"
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}
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},
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{
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"endpoint":"endpoint13",
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"host":"mem4",
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"memdev":{
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"memdev":"mem4",
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"pmem_size":"256.00 MiB (268.44 MB)",
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"ram_size":"256.00 MiB (268.44 MB)",
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"serial":"0x3",
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"numa_node":1,
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"host":"cxl_mem.3"
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}
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}
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]
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}
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]
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},
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{
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"port":"port4",
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"host":"cxl_host_bridge.0",
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"ports:port4":[
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{
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"port":"port6",
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"host":"cxl_switch_uport.0",
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"endpoints:port6":[
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{
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"endpoint":"endpoint7",
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"host":"mem1",
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"memdev":{
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"memdev":"mem1",
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"pmem_size":"256.00 MiB (268.44 MB)",
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"ram_size":"256.00 MiB (268.44 MB)",
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"serial":"0",
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"numa_node":0,
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"host":"cxl_mem.0"
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}
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},
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{
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"endpoint":"endpoint14",
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"host":"mem5",
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"memdev":{
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"memdev":"mem5",
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"pmem_size":"256.00 MiB (268.44 MB)",
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"ram_size":"256.00 MiB (268.44 MB)",
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"serial":"0x4",
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"numa_node":0,
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"host":"cxl_mem.4"
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}
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}
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]
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},
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{
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"port":"port10",
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"host":"cxl_switch_uport.2",
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"endpoints:port10":[
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{
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"endpoint":"endpoint16",
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"host":"mem7",
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"memdev":{
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"memdev":"mem7",
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"pmem_size":"256.00 MiB (268.44 MB)",
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"ram_size":"256.00 MiB (268.44 MB)",
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"serial":"0x6",
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"numa_node":0,
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"host":"cxl_mem.6"
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}
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},
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{
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"endpoint":"endpoint11",
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"host":"mem3",
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"memdev":{
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"memdev":"mem3",
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"pmem_size":"256.00 MiB (268.44 MB)",
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"ram_size":"256.00 MiB (268.44 MB)",
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"serial":"0x2",
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"numa_node":0,
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"host":"cxl_mem.2"
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}
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}
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]
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}
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]
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}
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]
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}
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In that listing each "root", "port", and "endpoint" object correspond a kernel
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'struct cxl_port' object. A 'cxl_port' is a device that can decode CXL.mem to
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its descendants. So "root" claims non-PCIe enumerable platform decode ranges and
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decodes them to "ports", "ports" decode to "endpoints", and "endpoints"
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represent the decode from SPA (System Physical Address) to DPA (Device Physical
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Address).
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Continuing the RAID analogy, disks have both topology metadata and on device
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metadata that determine RAID set assembly. CXL Port topology and CXL Port link
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status is metadata for CXL.mem set assembly. The CXL Port topology is enumerated
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by the arrival of a CXL.mem device. I.e. unless and until the PCIe core attaches
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the cxl_pci driver to a CXL Memory Expander there is no role for CXL Port
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objects. Conversely for hot-unplug / removal scenarios, there is no need for
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the Linux PCI core to tear down switch-level CXL resources because the endpoint
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->remove() event cleans up the port data that was established to support that
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Memory Expander.
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The port metadata and potential decode schemes that a give memory device may
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participate can be determined via a command like::
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# cxl list -BDMu -d root -m mem3
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{
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"bus":"root3",
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"provider":"cxl_test",
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"decoders:root3":[
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{
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"decoder":"decoder3.1",
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"resource":"0x8030000000",
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"size":"512.00 MiB (536.87 MB)",
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"volatile_capable":true,
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"nr_targets":2
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},
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{
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"decoder":"decoder3.3",
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"resource":"0x8060000000",
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"size":"512.00 MiB (536.87 MB)",
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"pmem_capable":true,
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"nr_targets":2
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},
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{
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"decoder":"decoder3.0",
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"resource":"0x8020000000",
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"size":"256.00 MiB (268.44 MB)",
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"volatile_capable":true,
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"nr_targets":1
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},
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{
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"decoder":"decoder3.2",
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"resource":"0x8050000000",
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"size":"256.00 MiB (268.44 MB)",
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"pmem_capable":true,
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"nr_targets":1
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}
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],
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"memdevs:root3":[
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{
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"memdev":"mem3",
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"pmem_size":"256.00 MiB (268.44 MB)",
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"ram_size":"256.00 MiB (268.44 MB)",
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"serial":"0x2",
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"numa_node":0,
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"host":"cxl_mem.2"
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}
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]
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}
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...which queries the CXL topology to ask "given CXL Memory Expander with a kernel
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device name of 'mem3' which platform level decode ranges may this device
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participate". A given expander can participate in multiple CXL.mem interleave
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sets simultaneously depending on how many decoder resource it has. In this
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example mem3 can participate in one or more of a PMEM interleave that spans to
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Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile
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memory interleave that spans 2 Host Bridges, and a Volatile memory interleave
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that only targets a single Host Bridge.
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Conversely the memory devices that can participate in a given platform level
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decode scheme can be determined via a command like the following::
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# cxl list -MDu -d 3.2
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[
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{
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"memdevs":[
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{
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"memdev":"mem1",
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"pmem_size":"256.00 MiB (268.44 MB)",
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"ram_size":"256.00 MiB (268.44 MB)",
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"serial":"0",
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"numa_node":0,
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"host":"cxl_mem.0"
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},
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{
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"memdev":"mem5",
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"pmem_size":"256.00 MiB (268.44 MB)",
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"ram_size":"256.00 MiB (268.44 MB)",
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"serial":"0x4",
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"numa_node":0,
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"host":"cxl_mem.4"
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},
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{
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"memdev":"mem7",
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"pmem_size":"256.00 MiB (268.44 MB)",
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"ram_size":"256.00 MiB (268.44 MB)",
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"serial":"0x6",
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"numa_node":0,
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"host":"cxl_mem.6"
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},
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{
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"memdev":"mem3",
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"pmem_size":"256.00 MiB (268.44 MB)",
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"ram_size":"256.00 MiB (268.44 MB)",
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"serial":"0x2",
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"numa_node":0,
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"host":"cxl_mem.2"
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}
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]
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},
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{
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"root decoders":[
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{
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"decoder":"decoder3.2",
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"resource":"0x8050000000",
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"size":"256.00 MiB (268.44 MB)",
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"pmem_capable":true,
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"nr_targets":1
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}
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]
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}
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]
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...where the naming scheme for decoders is "decoder<port_id>.<instance_id>".
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Driver Infrastructure
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=====================
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This section covers the driver infrastructure for a CXL memory device.
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CXL Memory Device
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-----------------
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.. kernel-doc:: drivers/cxl/pci.c
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:doc: cxl pci
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.. kernel-doc:: drivers/cxl/pci.c
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:internal:
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.. kernel-doc:: drivers/cxl/mem.c
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:doc: cxl mem
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CXL Port
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--------
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.. kernel-doc:: drivers/cxl/port.c
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:doc: cxl port
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CXL Core
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--------
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.. kernel-doc:: drivers/cxl/cxl.h
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:doc: cxl objects
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.. kernel-doc:: drivers/cxl/cxl.h
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:internal:
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.. kernel-doc:: drivers/cxl/core/port.c
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:doc: cxl core
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.. kernel-doc:: drivers/cxl/core/port.c
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:identifiers:
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.. kernel-doc:: drivers/cxl/core/pci.c
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:doc: cxl core pci
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.. kernel-doc:: drivers/cxl/core/pci.c
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:identifiers:
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.. kernel-doc:: drivers/cxl/core/pmem.c
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:doc: cxl pmem
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.. kernel-doc:: drivers/cxl/core/regs.c
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:doc: cxl registers
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.. kernel-doc:: drivers/cxl/core/mbox.c
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:doc: cxl mbox
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CXL Regions
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-----------
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.. kernel-doc:: drivers/cxl/core/region.c
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:doc: cxl core region
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.. kernel-doc:: drivers/cxl/core/region.c
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:identifiers:
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External Interfaces
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===================
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CXL IOCTL Interface
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-------------------
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.. kernel-doc:: include/uapi/linux/cxl_mem.h
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:doc: UAPI
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.. kernel-doc:: include/uapi/linux/cxl_mem.h
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:internal:
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