238 lines
3.5 KiB
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238 lines
3.5 KiB
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===========
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DC Glossary
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===========
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On this page, we try to keep track of acronyms related to the display
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component. If you do not find what you are looking for, look at the
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'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
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consider asking in the amdgfx and update this page.
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.. glossary::
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ABM
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Adaptive Backlight Modulation
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APU
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Accelerated Processing Unit
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ASIC
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Application-Specific Integrated Circuit
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ASSR
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Alternate Scrambler Seed Reset
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AZ
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Azalia (HD audio DMA engine)
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BPC
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Bits Per Colour/Component
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BPP
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Bits Per Pixel
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Clocks
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* PCLK: Pixel Clock
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* SYMCLK: Symbol Clock
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* SOCCLK: GPU Engine Clock
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* DISPCLK: Display Clock
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* DPPCLK: DPP Clock
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* DCFCLK: Display Controller Fabric Clock
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* REFCLK: Real Time Reference Clock
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* PPLL: Pixel PLL
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* FCLK: Fabric Clock
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* MCLK: Memory Clock
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CRC
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Cyclic Redundancy Check
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CRTC
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Cathode Ray Tube Controller - commonly called "Controller" - Generates
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raw stream of pixels, clocked at pixel clock
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CVT
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Coordinated Video Timings
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DAL
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Display Abstraction layer
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DC (Software)
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Display Core
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DC (Hardware)
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Display Controller
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DCC
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Delta Colour Compression
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DCE
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Display Controller Engine
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DCHUB
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Display Controller HUB
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ARB
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Arbiter
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VTG
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Vertical Timing Generator
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DCN
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Display Core Next
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DCCG
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Display Clock Generator block
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DDC
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Display Data Channel
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DIO
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Display IO
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DPP
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Display Pipes and Planes
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DSC
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Display Stream Compression (Reduce the amount of bits to represent pixel
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count while at the same pixel clock)
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dGPU
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discrete GPU
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DMIF
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Display Memory Interface
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DML
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Display Mode Library
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DMCU
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Display Micro-Controller Unit
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DMCUB
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Display Micro-Controller Unit, version B
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DPCD
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DisplayPort Configuration Data
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DPM(S)
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Display Power Management (Signaling)
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DRR
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Dynamic Refresh Rate
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DWB
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Display Writeback
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FB
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Frame Buffer
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FBC
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Frame Buffer Compression
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FEC
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Forward Error Correction
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FRL
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Fixed Rate Link
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GCO
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Graphical Controller Object
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GSL
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Global Swap Lock
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iGPU
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integrated GPU
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ISR
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Interrupt Service Request
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ISV
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Independent Software Vendor
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KMD
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Kernel Mode Driver
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LB
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Line Buffer
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LFC
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Low Framerate Compensation
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LTTPR
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Link Training Tunable Phy Repeater
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LUT
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Lookup Table
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MALL
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Memory Access at Last Level
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MC
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Memory Controller
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MPC/MPCC
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Multiple pipes and plane combine
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MPO
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Multi Plane Overlay
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MST
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Multi Stream Transport
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NBP State
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Northbridge Power State
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NBIO
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North Bridge Input/Output
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ODM
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Output Data Mapping
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OPM
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Output Protection Manager
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OPP
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Output Plane Processor
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OPTC
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Output Pipe Timing Combiner
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OTG
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Output Timing Generator
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PCON
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Power Controller
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PGFSM
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Power Gate Finite State Machine
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PSR
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Panel Self Refresh
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SCL
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Scaler
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SDP
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Scalable Data Port
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SLS
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Single Large Surface
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SST
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Single Stream Transport
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TMDS
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Transition-Minimized Differential Signaling
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TMZ
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Trusted Memory Zone
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TTU
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Time to Underflow
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VRR
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Variable Refresh Rate
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UVD
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Unified Video Decoder
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