2023-08-30 17:31:07 +02:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP ZCU102 RevB
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*
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2023-10-24 12:59:35 +02:00
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* (C) Copyright 2016 - 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
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2023-08-30 17:31:07 +02:00
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*
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2023-10-24 12:59:35 +02:00
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* Michal Simek <michal.simek@amd.com>
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2023-08-30 17:31:07 +02:00
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*/
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#include "zynqmp-zcu102-revA.dts"
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/ {
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model = "ZynqMP ZCU102 RevB";
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compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
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};
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&gem3 {
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phy-handle = <&phyc>;
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2023-10-24 12:59:35 +02:00
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mdio: mdio {
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phyc: ethernet-phy@c {
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#phy-cells = <0x1>;
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compatible = "ethernet-phy-id2000.a231";
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
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};
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/* Cleanup from RevA */
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/delete-node/ ethernet-phy@21;
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2023-08-30 17:31:07 +02:00
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};
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};
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/* Fix collision with u61 */
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&i2c0 {
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i2c-mux@75 {
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i2c@2 {
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max15303@1b { /* u8 */
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compatible = "maxim,max15303";
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reg = <0x1b>;
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};
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/delete-node/ max15303@20;
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};
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};
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};
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