203 lines
4.3 KiB
C
203 lines
4.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_CSKY_ATOMIC_H
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#define __ASM_CSKY_ATOMIC_H
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#ifdef CONFIG_SMP
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#include <asm-generic/atomic64.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#define __atomic_acquire_fence() __bar_brarw()
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#define __atomic_release_fence() __bar_brwaw()
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static __always_inline int arch_atomic_read(const atomic_t *v)
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{
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return READ_ONCE(v->counter);
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}
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static __always_inline void arch_atomic_set(atomic_t *v, int i)
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{
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WRITE_ONCE(v->counter, i);
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}
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#define ATOMIC_OP(op) \
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static __always_inline \
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void arch_atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned long tmp; \
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__asm__ __volatile__ ( \
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"1: ldex.w %0, (%2) \n" \
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" " #op " %0, %1 \n" \
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" stex.w %0, (%2) \n" \
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" bez %0, 1b \n" \
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: "=&r" (tmp) \
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: "r" (i), "r" (&v->counter) \
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: "memory"); \
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}
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ATOMIC_OP(add)
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ATOMIC_OP(sub)
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ATOMIC_OP(and)
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ATOMIC_OP( or)
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ATOMIC_OP(xor)
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#undef ATOMIC_OP
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#define ATOMIC_FETCH_OP(op) \
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static __always_inline \
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int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
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{ \
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register int ret, tmp; \
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__asm__ __volatile__ ( \
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"1: ldex.w %0, (%3) \n" \
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" mov %1, %0 \n" \
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" " #op " %0, %2 \n" \
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" stex.w %0, (%3) \n" \
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" bez %0, 1b \n" \
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: "=&r" (tmp), "=&r" (ret) \
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: "r" (i), "r"(&v->counter) \
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: "memory"); \
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return ret; \
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}
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#define ATOMIC_OP_RETURN(op, c_op) \
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static __always_inline \
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int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
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{ \
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return arch_atomic_fetch_##op##_relaxed(i, v) c_op i; \
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}
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#define ATOMIC_OPS(op, c_op) \
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ATOMIC_FETCH_OP(op) \
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ATOMIC_OP_RETURN(op, c_op)
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ATOMIC_OPS(add, +)
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ATOMIC_OPS(sub, -)
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#define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed
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#define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed
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#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
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#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
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#undef ATOMIC_OPS
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#undef ATOMIC_OP_RETURN
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#define ATOMIC_OPS(op) \
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ATOMIC_FETCH_OP(op)
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ATOMIC_OPS(and)
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ATOMIC_OPS( or)
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ATOMIC_OPS(xor)
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#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
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#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
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#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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static __always_inline int
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arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
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{
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int prev, tmp;
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__asm__ __volatile__ (
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RELEASE_FENCE
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"1: ldex.w %0, (%3) \n"
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" cmpne %0, %4 \n"
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" bf 2f \n"
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" mov %1, %0 \n"
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" add %1, %2 \n"
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" stex.w %1, (%3) \n"
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" bez %1, 1b \n"
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FULL_FENCE
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"2:\n"
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: "=&r" (prev), "=&r" (tmp)
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: "r" (a), "r" (&v->counter), "r" (u)
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: "memory");
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return prev;
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}
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#define arch_atomic_fetch_add_unless arch_atomic_fetch_add_unless
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static __always_inline bool
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arch_atomic_inc_unless_negative(atomic_t *v)
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{
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int rc, tmp;
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__asm__ __volatile__ (
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RELEASE_FENCE
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"1: ldex.w %0, (%2) \n"
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" movi %1, 0 \n"
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" blz %0, 2f \n"
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" movi %1, 1 \n"
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" addi %0, 1 \n"
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" stex.w %0, (%2) \n"
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" bez %0, 1b \n"
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FULL_FENCE
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"2:\n"
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: "=&r" (tmp), "=&r" (rc)
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: "r" (&v->counter)
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: "memory");
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return tmp ? true : false;
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}
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#define arch_atomic_inc_unless_negative arch_atomic_inc_unless_negative
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static __always_inline bool
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arch_atomic_dec_unless_positive(atomic_t *v)
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{
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int rc, tmp;
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__asm__ __volatile__ (
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RELEASE_FENCE
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"1: ldex.w %0, (%2) \n"
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" movi %1, 0 \n"
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" bhz %0, 2f \n"
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" movi %1, 1 \n"
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" subi %0, 1 \n"
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" stex.w %0, (%2) \n"
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" bez %0, 1b \n"
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FULL_FENCE
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"2:\n"
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: "=&r" (tmp), "=&r" (rc)
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: "r" (&v->counter)
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: "memory");
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return tmp ? true : false;
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}
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#define arch_atomic_dec_unless_positive arch_atomic_dec_unless_positive
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static __always_inline int
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arch_atomic_dec_if_positive(atomic_t *v)
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{
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int dec, tmp;
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__asm__ __volatile__ (
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RELEASE_FENCE
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"1: ldex.w %0, (%2) \n"
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" subi %1, %0, 1 \n"
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" blz %1, 2f \n"
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" stex.w %1, (%2) \n"
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" bez %1, 1b \n"
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FULL_FENCE
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"2:\n"
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: "=&r" (dec), "=&r" (tmp)
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: "r" (&v->counter)
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: "memory");
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return dec - 1;
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}
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#define arch_atomic_dec_if_positive arch_atomic_dec_if_positive
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#else
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#include <asm-generic/atomic.h>
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#endif
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#endif /* __ASM_CSKY_ATOMIC_H */
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