2023-08-30 17:31:07 +02:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Standard user space access functions based on mvcp/mvcs and doing
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* interesting things in the secondary space mode.
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*
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* Copyright IBM Corp. 2006,2014
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* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
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* Gerald Schaefer (gerald.schaefer@de.ibm.com)
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*/
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#include <linux/uaccess.h>
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#include <linux/export.h>
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#include <linux/mm.h>
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#include <asm/asm-extable.h>
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#ifdef CONFIG_DEBUG_ENTRY
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void debug_user_asce(int exit)
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{
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unsigned long cr1, cr7;
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__ctl_store(cr1, 1, 1);
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__ctl_store(cr7, 7, 7);
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if (cr1 == S390_lowcore.kernel_asce && cr7 == S390_lowcore.user_asce)
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return;
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panic("incorrect ASCE on kernel %s\n"
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"cr1: %016lx cr7: %016lx\n"
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"kernel: %016llx user: %016llx\n",
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exit ? "exit" : "entry", cr1, cr7,
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S390_lowcore.kernel_asce, S390_lowcore.user_asce);
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}
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#endif /*CONFIG_DEBUG_ENTRY */
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static unsigned long raw_copy_from_user_key(void *to, const void __user *from,
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unsigned long size, unsigned long key)
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{
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2023-10-24 12:59:35 +02:00
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unsigned long rem;
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2023-08-30 17:31:07 +02:00
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union oac spec = {
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.oac2.key = key,
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.oac2.as = PSW_BITS_AS_SECONDARY,
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.oac2.k = 1,
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.oac2.a = 1,
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};
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asm volatile(
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2023-10-24 12:59:35 +02:00
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" lr 0,%[spec]\n"
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"0: mvcos 0(%[to]),0(%[from]),%[size]\n"
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"1: jz 5f\n"
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" algr %[size],%[val]\n"
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" slgr %[from],%[val]\n"
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" slgr %[to],%[val]\n"
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" j 0b\n"
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"2: la %[rem],4095(%[from])\n" /* rem = from + 4095 */
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" nr %[rem],%[val]\n" /* rem = (from + 4095) & -4096 */
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" slgr %[rem],%[from]\n"
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" clgr %[size],%[rem]\n" /* copy crosses next page boundary? */
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" jnh 6f\n"
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"3: mvcos 0(%[to]),0(%[from]),%[rem]\n"
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"4: slgr %[size],%[rem]\n"
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" j 6f\n"
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"5: slgr %[size],%[size]\n"
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"6:\n"
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EX_TABLE(0b, 2b)
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EX_TABLE(1b, 2b)
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EX_TABLE(3b, 6b)
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EX_TABLE(4b, 6b)
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: [size] "+&a" (size), [from] "+&a" (from), [to] "+&a" (to), [rem] "=&a" (rem)
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: [val] "a" (-4096UL), [spec] "d" (spec.val)
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2023-08-30 17:31:07 +02:00
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: "cc", "memory", "0");
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return size;
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}
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unsigned long raw_copy_from_user(void *to, const void __user *from, unsigned long n)
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{
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return raw_copy_from_user_key(to, from, n, 0);
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}
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EXPORT_SYMBOL(raw_copy_from_user);
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unsigned long _copy_from_user_key(void *to, const void __user *from,
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unsigned long n, unsigned long key)
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{
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unsigned long res = n;
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might_fault();
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if (!should_fail_usercopy()) {
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instrument_copy_from_user_before(to, from, n);
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res = raw_copy_from_user_key(to, from, n, key);
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instrument_copy_from_user_after(to, from, n, res);
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}
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if (unlikely(res))
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memset(to + (n - res), 0, res);
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return res;
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}
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EXPORT_SYMBOL(_copy_from_user_key);
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static unsigned long raw_copy_to_user_key(void __user *to, const void *from,
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unsigned long size, unsigned long key)
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{
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2023-10-24 12:59:35 +02:00
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unsigned long rem;
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2023-08-30 17:31:07 +02:00
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union oac spec = {
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.oac1.key = key,
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.oac1.as = PSW_BITS_AS_SECONDARY,
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.oac1.k = 1,
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.oac1.a = 1,
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};
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asm volatile(
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2023-10-24 12:59:35 +02:00
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" lr 0,%[spec]\n"
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"0: mvcos 0(%[to]),0(%[from]),%[size]\n"
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"1: jz 5f\n"
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" algr %[size],%[val]\n"
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" slgr %[to],%[val]\n"
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" slgr %[from],%[val]\n"
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" j 0b\n"
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"2: la %[rem],4095(%[to])\n" /* rem = to + 4095 */
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" nr %[rem],%[val]\n" /* rem = (to + 4095) & -4096 */
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" slgr %[rem],%[to]\n"
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" clgr %[size],%[rem]\n" /* copy crosses next page boundary? */
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" jnh 6f\n"
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"3: mvcos 0(%[to]),0(%[from]),%[rem]\n"
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"4: slgr %[size],%[rem]\n"
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" j 6f\n"
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"5: slgr %[size],%[size]\n"
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"6:\n"
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EX_TABLE(0b, 2b)
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EX_TABLE(1b, 2b)
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EX_TABLE(3b, 6b)
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EX_TABLE(4b, 6b)
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: [size] "+&a" (size), [to] "+&a" (to), [from] "+&a" (from), [rem] "=&a" (rem)
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: [val] "a" (-4096UL), [spec] "d" (spec.val)
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2023-08-30 17:31:07 +02:00
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: "cc", "memory", "0");
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return size;
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}
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unsigned long raw_copy_to_user(void __user *to, const void *from, unsigned long n)
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{
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return raw_copy_to_user_key(to, from, n, 0);
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}
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EXPORT_SYMBOL(raw_copy_to_user);
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unsigned long _copy_to_user_key(void __user *to, const void *from,
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unsigned long n, unsigned long key)
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{
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might_fault();
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if (should_fail_usercopy())
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return n;
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instrument_copy_to_user(to, from, n);
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return raw_copy_to_user_key(to, from, n, key);
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}
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EXPORT_SYMBOL(_copy_to_user_key);
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unsigned long __clear_user(void __user *to, unsigned long size)
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{
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unsigned long rem;
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union oac spec = {
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.oac1.as = PSW_BITS_AS_SECONDARY,
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.oac1.a = 1,
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};
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asm volatile(
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2023-10-24 12:59:35 +02:00
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" lr 0,%[spec]\n"
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"0: mvcos 0(%[to]),0(%[zeropg]),%[size]\n"
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"1: jz 5f\n"
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" algr %[size],%[val]\n"
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" slgr %[to],%[val]\n"
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" j 0b\n"
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"2: la %[rem],4095(%[to])\n" /* rem = to + 4095 */
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" nr %[rem],%[val]\n" /* rem = (to + 4095) & -4096 */
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" slgr %[rem],%[to]\n"
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" clgr %[size],%[rem]\n" /* copy crosses next page boundary? */
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" jnh 6f\n"
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"3: mvcos 0(%[to]),0(%[zeropg]),%[rem]\n"
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"4: slgr %[size],%[rem]\n"
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" j 6f\n"
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"5: slgr %[size],%[size]\n"
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"6:\n"
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EX_TABLE(0b, 2b)
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EX_TABLE(1b, 2b)
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EX_TABLE(3b, 6b)
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EX_TABLE(4b, 6b)
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: [size] "+&a" (size), [to] "+&a" (to), [rem] "=&a" (rem)
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: [val] "a" (-4096UL), [zeropg] "a" (empty_zero_page), [spec] "d" (spec.val)
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2023-08-30 17:31:07 +02:00
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: "cc", "memory", "0");
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return size;
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}
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EXPORT_SYMBOL(__clear_user);
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