2023-08-30 17:31:07 +02:00
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_CPU_H
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#define _ASM_X86_CPU_H
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#include <linux/device.h>
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#include <linux/cpu.h>
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#include <linux/topology.h>
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#include <linux/nodemask.h>
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#include <linux/percpu.h>
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#include <asm/ibt.h>
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#ifdef CONFIG_SMP
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extern void prefill_possible_map(void);
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#else /* CONFIG_SMP */
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static inline void prefill_possible_map(void) {}
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#define cpu_physical_id(cpu) boot_cpu_physical_apicid
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#define cpu_acpi_id(cpu) 0
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#define safe_smp_processor_id() 0
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#endif /* CONFIG_SMP */
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struct x86_cpu {
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struct cpu cpu;
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};
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#ifdef CONFIG_HOTPLUG_CPU
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extern int arch_register_cpu(int num);
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extern void arch_unregister_cpu(int);
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2023-10-24 12:59:35 +02:00
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extern void soft_restart_cpu(void);
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2023-08-30 17:31:07 +02:00
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#endif
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extern void ap_init_aperfmperf(void);
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int mwait_usable(const struct cpuinfo_x86 *);
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unsigned int x86_family(unsigned int sig);
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unsigned int x86_model(unsigned int sig);
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unsigned int x86_stepping(unsigned int sig);
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#ifdef CONFIG_CPU_SUP_INTEL
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extern void __init sld_setup(struct cpuinfo_x86 *c);
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extern bool handle_user_split_lock(struct pt_regs *regs, long error_code);
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extern bool handle_guest_split_lock(unsigned long ip);
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extern void handle_bus_lock(struct pt_regs *regs);
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u8 get_this_hybrid_cpu_type(void);
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#else
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static inline void __init sld_setup(struct cpuinfo_x86 *c) {}
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static inline bool handle_user_split_lock(struct pt_regs *regs, long error_code)
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{
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return false;
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}
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static inline bool handle_guest_split_lock(unsigned long ip)
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{
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return false;
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}
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static inline void handle_bus_lock(struct pt_regs *regs) {}
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static inline u8 get_this_hybrid_cpu_type(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_IA32_FEAT_CTL
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void init_ia32_feat_ctl(struct cpuinfo_x86 *c);
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#else
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static inline void init_ia32_feat_ctl(struct cpuinfo_x86 *c) {}
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#endif
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extern __noendbr void cet_disable(void);
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struct ucode_cpu_info;
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int intel_cpu_collect_info(struct ucode_cpu_info *uci);
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static inline bool intel_cpu_signatures_match(unsigned int s1, unsigned int p1,
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unsigned int s2, unsigned int p2)
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{
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if (s1 != s2)
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return false;
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/* Processor flags are either both 0 ... */
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if (!p1 && !p2)
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return true;
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/* ... or they intersect. */
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return p1 & p2;
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}
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extern u64 x86_read_arch_cap_msr(void);
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int intel_find_matching_signature(void *mc, unsigned int csig, int cpf);
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int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type);
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2023-10-24 12:59:35 +02:00
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extern struct cpumask cpus_stop_mask;
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2023-08-30 17:31:07 +02:00
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#endif /* _ASM_X86_CPU_H */
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