2023-08-30 17:31:07 +02:00
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/dma-map-ops.h>
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#include <linux/dma-direct.h>
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#include <linux/iommu.h>
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#include <linux/dmar.h>
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#include <linux/export.h>
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#include <linux/memblock.h>
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#include <linux/gfp.h>
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#include <linux/pci.h>
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#include <linux/amd-iommu.h>
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#include <asm/proto.h>
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#include <asm/dma.h>
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#include <asm/iommu.h>
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#include <asm/gart.h>
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#include <asm/x86_init.h>
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#include <xen/xen.h>
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#include <xen/swiotlb-xen.h>
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static bool disable_dac_quirk __read_mostly;
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const struct dma_map_ops *dma_ops;
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EXPORT_SYMBOL(dma_ops);
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#ifdef CONFIG_IOMMU_DEBUG
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int panic_on_overflow __read_mostly = 1;
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int force_iommu __read_mostly = 1;
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#else
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int panic_on_overflow __read_mostly = 0;
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int force_iommu __read_mostly = 0;
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#endif
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int iommu_merge __read_mostly = 0;
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int no_iommu __read_mostly;
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/* Set this to 1 if there is a HW IOMMU in the system */
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int iommu_detected __read_mostly = 0;
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#ifdef CONFIG_SWIOTLB
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bool x86_swiotlb_enable;
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static unsigned int x86_swiotlb_flags;
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static void __init pci_swiotlb_detect(void)
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{
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/* don't initialize swiotlb if iommu=off (no_iommu=1) */
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if (!no_iommu && max_possible_pfn > MAX_DMA32_PFN)
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x86_swiotlb_enable = true;
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/*
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* Set swiotlb to 1 so that bounce buffers are allocated and used for
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* devices that can't support DMA to encrypted memory.
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*/
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if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT))
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x86_swiotlb_enable = true;
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/*
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* Guest with guest memory encryption currently perform all DMA through
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* bounce buffers as the hypervisor can't access arbitrary VM memory
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* that is not explicitly shared with it.
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*/
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if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) {
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x86_swiotlb_enable = true;
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x86_swiotlb_flags |= SWIOTLB_FORCE;
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}
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}
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#else
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static inline void __init pci_swiotlb_detect(void)
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{
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}
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#define x86_swiotlb_flags 0
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#endif /* CONFIG_SWIOTLB */
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#ifdef CONFIG_SWIOTLB_XEN
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static void __init pci_xen_swiotlb_init(void)
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{
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if (!xen_initial_domain() && !x86_swiotlb_enable)
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return;
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x86_swiotlb_enable = true;
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x86_swiotlb_flags |= SWIOTLB_ANY;
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swiotlb_init_remap(true, x86_swiotlb_flags, xen_swiotlb_fixup);
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dma_ops = &xen_swiotlb_dma_ops;
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if (IS_ENABLED(CONFIG_PCI))
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pci_request_acs();
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}
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int pci_xen_swiotlb_init_late(void)
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{
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if (dma_ops == &xen_swiotlb_dma_ops)
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return 0;
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/* we can work with the default swiotlb */
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if (!io_tlb_default_mem.nslabs) {
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int rc = swiotlb_init_late(swiotlb_size_or_default(),
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GFP_KERNEL, xen_swiotlb_fixup);
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if (rc < 0)
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return rc;
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}
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/* XXX: this switches the dma ops under live devices! */
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dma_ops = &xen_swiotlb_dma_ops;
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if (IS_ENABLED(CONFIG_PCI))
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pci_request_acs();
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_xen_swiotlb_init_late);
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#else
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static inline void __init pci_xen_swiotlb_init(void)
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{
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}
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#endif /* CONFIG_SWIOTLB_XEN */
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void __init pci_iommu_alloc(void)
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{
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if (xen_pv_domain()) {
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pci_xen_swiotlb_init();
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return;
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}
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pci_swiotlb_detect();
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gart_iommu_hole_init();
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amd_iommu_detect();
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detect_intel_iommu();
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swiotlb_init(x86_swiotlb_enable, x86_swiotlb_flags);
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}
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/*
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2023-10-24 12:59:35 +02:00
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* See <Documentation/arch/x86/x86_64/boot-options.rst> for the iommu kernel
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2023-08-30 17:31:07 +02:00
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* parameter documentation.
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*/
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static __init int iommu_setup(char *p)
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{
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iommu_merge = 1;
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if (!p)
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return -EINVAL;
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while (*p) {
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if (!strncmp(p, "off", 3))
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no_iommu = 1;
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/* gart_parse_options has more force support */
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if (!strncmp(p, "force", 5))
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force_iommu = 1;
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if (!strncmp(p, "noforce", 7)) {
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iommu_merge = 0;
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force_iommu = 0;
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}
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if (!strncmp(p, "biomerge", 8)) {
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iommu_merge = 1;
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force_iommu = 1;
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}
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if (!strncmp(p, "panic", 5))
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panic_on_overflow = 1;
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if (!strncmp(p, "nopanic", 7))
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panic_on_overflow = 0;
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if (!strncmp(p, "merge", 5)) {
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iommu_merge = 1;
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force_iommu = 1;
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}
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if (!strncmp(p, "nomerge", 7))
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iommu_merge = 0;
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if (!strncmp(p, "forcesac", 8))
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pr_warn("forcesac option ignored.\n");
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if (!strncmp(p, "allowdac", 8))
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pr_warn("allowdac option ignored.\n");
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if (!strncmp(p, "nodac", 5))
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pr_warn("nodac option ignored.\n");
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if (!strncmp(p, "usedac", 6)) {
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disable_dac_quirk = true;
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return 1;
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}
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#ifdef CONFIG_SWIOTLB
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if (!strncmp(p, "soft", 4))
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x86_swiotlb_enable = true;
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#endif
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if (!strncmp(p, "pt", 2))
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iommu_set_default_passthrough(true);
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if (!strncmp(p, "nopt", 4))
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iommu_set_default_translated(true);
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gart_parse_options(p);
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p += strcspn(p, ",");
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if (*p == ',')
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++p;
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}
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return 0;
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}
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early_param("iommu", iommu_setup);
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static int __init pci_iommu_init(void)
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{
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x86_init.iommu.iommu_init();
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#ifdef CONFIG_SWIOTLB
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/* An IOMMU turned us off. */
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if (x86_swiotlb_enable) {
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pr_info("PCI-DMA: Using software bounce buffering for IO (SWIOTLB)\n");
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swiotlb_print_info();
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} else {
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swiotlb_exit();
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}
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#endif
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return 0;
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}
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/* Must execute after PCI subsystem */
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rootfs_initcall(pci_iommu_init);
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#ifdef CONFIG_PCI
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/* Many VIA bridges seem to corrupt data for DAC. Disable it here */
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static int via_no_dac_cb(struct pci_dev *pdev, void *data)
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{
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pdev->dev.bus_dma_limit = DMA_BIT_MASK(32);
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return 0;
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}
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static void via_no_dac(struct pci_dev *dev)
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{
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if (!disable_dac_quirk) {
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dev_info(&dev->dev, "disabling DAC on VIA PCI bridge\n");
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pci_walk_bus(dev->subordinate, via_no_dac_cb, NULL);
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}
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}
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DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
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PCI_CLASS_BRIDGE_PCI, 8, via_no_dac);
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#endif
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