237 lines
7.1 KiB
C
237 lines
7.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* TSC frequency enumeration via MSR
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*
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* Copyright (C) 2013, 2018 Intel Corporation
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* Author: Bin Gao <bin.gao@intel.com>
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*/
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#include <linux/kernel.h>
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#include <linux/thread_info.h>
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#include <asm/apic.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/msr.h>
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#include <asm/param.h>
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#include <asm/tsc.h>
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#define MAX_NUM_FREQS 16 /* 4 bits to select the frequency */
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/*
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* The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
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* lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs
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* use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
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* is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
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* unclear if the root PLL outputs are used directly by the CPU clock PLL or
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* if there is another PLL in between.
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* This does not matter though, we can model the chain of PLLs as a single PLL
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* with a quotient equal to the quotients of all PLLs in the chain multiplied.
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* So we can create a simplified model of the CPU clock setup using a reference
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* clock of 100 MHz plus a quotient which gets us as close to the frequency
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* from the SDM as possible.
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* For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
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* 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
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*/
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#define TSC_REFERENCE_KHZ 100000
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struct muldiv {
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u32 multiplier;
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u32 divider;
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};
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/*
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* If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
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* read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
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* Unfortunately some Intel Atom SoCs aren't quite compliant to this,
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* so we need manually differentiate SoC families. This is what the
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* field use_msr_plat does.
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*/
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struct freq_desc {
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bool use_msr_plat;
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struct muldiv muldiv[MAX_NUM_FREQS];
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/*
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* Some CPU frequencies in the SDM do not map to known PLL freqs, in
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* that case the muldiv array is empty and the freqs array is used.
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*/
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u32 freqs[MAX_NUM_FREQS];
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u32 mask;
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};
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/*
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* Penwell and Clovertrail use spread spectrum clock,
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* so the freq number is not exactly the same as reported
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* by MSR based on SDM.
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*/
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static const struct freq_desc freq_desc_pnw = {
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.use_msr_plat = false,
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.freqs = { 0, 0, 0, 0, 0, 99840, 0, 83200 },
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.mask = 0x07,
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};
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static const struct freq_desc freq_desc_clv = {
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.use_msr_plat = false,
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.freqs = { 0, 133200, 0, 0, 0, 99840, 0, 83200 },
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.mask = 0x07,
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};
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/*
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* Bay Trail SDM MSR_FSB_FREQ frequencies simplified PLL model:
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* 000: 100 * 5 / 6 = 83.3333 MHz
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* 001: 100 * 1 / 1 = 100.0000 MHz
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* 010: 100 * 4 / 3 = 133.3333 MHz
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* 011: 100 * 7 / 6 = 116.6667 MHz
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* 100: 100 * 4 / 5 = 80.0000 MHz
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*/
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static const struct freq_desc freq_desc_byt = {
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.use_msr_plat = true,
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.muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 7, 6 },
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{ 4, 5 } },
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.mask = 0x07,
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};
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/*
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* Cherry Trail SDM MSR_FSB_FREQ frequencies simplified PLL model:
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* 0000: 100 * 5 / 6 = 83.3333 MHz
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* 0001: 100 * 1 / 1 = 100.0000 MHz
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* 0010: 100 * 4 / 3 = 133.3333 MHz
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* 0011: 100 * 7 / 6 = 116.6667 MHz
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* 0100: 100 * 4 / 5 = 80.0000 MHz
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* 0101: 100 * 14 / 15 = 93.3333 MHz
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* 0110: 100 * 9 / 10 = 90.0000 MHz
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* 0111: 100 * 8 / 9 = 88.8889 MHz
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* 1000: 100 * 7 / 8 = 87.5000 MHz
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*/
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static const struct freq_desc freq_desc_cht = {
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.use_msr_plat = true,
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.muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 7, 6 },
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{ 4, 5 }, { 14, 15 }, { 9, 10 }, { 8, 9 },
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{ 7, 8 } },
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.mask = 0x0f,
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};
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/*
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* Merriefield SDM MSR_FSB_FREQ frequencies simplified PLL model:
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* 0001: 100 * 1 / 1 = 100.0000 MHz
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* 0010: 100 * 4 / 3 = 133.3333 MHz
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*/
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static const struct freq_desc freq_desc_tng = {
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.use_msr_plat = true,
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.muldiv = { { 0, 0 }, { 1, 1 }, { 4, 3 } },
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.mask = 0x07,
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};
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/*
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* Moorefield SDM MSR_FSB_FREQ frequencies simplified PLL model:
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* 0000: 100 * 5 / 6 = 83.3333 MHz
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* 0001: 100 * 1 / 1 = 100.0000 MHz
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* 0010: 100 * 4 / 3 = 133.3333 MHz
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* 0011: 100 * 1 / 1 = 100.0000 MHz
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*/
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static const struct freq_desc freq_desc_ann = {
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.use_msr_plat = true,
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.muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 1, 1 } },
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.mask = 0x0f,
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};
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/*
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* 24 MHz crystal? : 24 * 13 / 4 = 78 MHz
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* Frequency step for Lightning Mountain SoC is fixed to 78 MHz,
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* so all the frequency entries are 78000.
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*/
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static const struct freq_desc freq_desc_lgm = {
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.use_msr_plat = true,
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.freqs = { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000,
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78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 },
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.mask = 0x0f,
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};
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static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_MID, &freq_desc_pnw),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_TABLET,&freq_desc_clv),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &freq_desc_byt),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &freq_desc_tng),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &freq_desc_cht),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_MID, &freq_desc_ann),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_NP, &freq_desc_lgm),
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{}
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};
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/*
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* MSR-based CPU/TSC frequency discovery for certain CPUs.
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*
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* Set global "lapic_timer_period" to bus_clock_cycles/jiffy
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* Return processor base frequency in KHz, or 0 on failure.
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*/
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unsigned long cpu_khz_from_msr(void)
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{
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u32 lo, hi, ratio, freq, tscref;
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const struct freq_desc *freq_desc;
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const struct x86_cpu_id *id;
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const struct muldiv *md;
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unsigned long res;
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int index;
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id = x86_match_cpu(tsc_msr_cpu_ids);
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if (!id)
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return 0;
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freq_desc = (struct freq_desc *)id->driver_data;
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if (freq_desc->use_msr_plat) {
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rdmsr(MSR_PLATFORM_INFO, lo, hi);
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ratio = (lo >> 8) & 0xff;
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} else {
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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ratio = (hi >> 8) & 0x1f;
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}
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/* Get FSB FREQ ID */
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rdmsr(MSR_FSB_FREQ, lo, hi);
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index = lo & freq_desc->mask;
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md = &freq_desc->muldiv[index];
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/*
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* Note this also catches cases where the index points to an unpopulated
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* part of muldiv, in that case the else will set freq and res to 0.
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*/
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if (md->divider) {
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tscref = TSC_REFERENCE_KHZ * md->multiplier;
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freq = DIV_ROUND_CLOSEST(tscref, md->divider);
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/*
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* Multiplying by ratio before the division has better
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* accuracy than just calculating freq * ratio.
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*/
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res = DIV_ROUND_CLOSEST(tscref * ratio, md->divider);
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} else {
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freq = freq_desc->freqs[index];
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res = freq * ratio;
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}
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if (freq == 0)
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pr_err("Error MSR_FSB_FREQ index %d is unknown\n", index);
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#ifdef CONFIG_X86_LOCAL_APIC
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lapic_timer_period = (freq * 1000) / HZ;
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#endif
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/*
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* TSC frequency determined by MSR is always considered "known"
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* because it is reported by HW.
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* Another fact is that on MSR capable platforms, PIT/HPET is
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* generally not available so calibration won't work at all.
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*/
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setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
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/*
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* Unfortunately there is no way for hardware to tell whether the
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* TSC is reliable. We were told by silicon design team that TSC
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* on Atom SoCs are always "reliable". TSC is also the only
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* reliable clocksource on these SoCs (HPET is either not present
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* or not functional) so mark TSC reliable which removes the
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* requirement for a watchdog clocksource.
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*/
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setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
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return res;
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}
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