280 lines
7.8 KiB
C
280 lines
7.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/spinlock.h>
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#include <linux/percpu.h>
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#include <linux/kallsyms.h>
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#include <linux/kcore.h>
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#include <linux/pgtable.h>
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#include <asm/cpu_entry_area.h>
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#include <asm/fixmap.h>
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#include <asm/desc.h>
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#include <asm/kasan.h>
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#include <asm/setup.h>
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static DEFINE_PER_CPU_PAGE_ALIGNED(struct entry_stack_page, entry_stack_storage);
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#ifdef CONFIG_X86_64
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static DEFINE_PER_CPU_PAGE_ALIGNED(struct exception_stacks, exception_stacks);
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DEFINE_PER_CPU(struct cea_exception_stacks*, cea_exception_stacks);
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static DEFINE_PER_CPU_READ_MOSTLY(unsigned long, _cea_offset);
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static __always_inline unsigned int cea_offset(unsigned int cpu)
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{
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return per_cpu(_cea_offset, cpu);
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}
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static __init void init_cea_offsets(void)
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{
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unsigned int max_cea;
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unsigned int i, j;
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if (!kaslr_enabled()) {
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for_each_possible_cpu(i)
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per_cpu(_cea_offset, i) = i;
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return;
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}
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max_cea = (CPU_ENTRY_AREA_MAP_SIZE - PAGE_SIZE) / CPU_ENTRY_AREA_SIZE;
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/* O(sodding terrible) */
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for_each_possible_cpu(i) {
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unsigned int cea;
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again:
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cea = get_random_u32_below(max_cea);
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for_each_possible_cpu(j) {
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if (cea_offset(j) == cea)
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goto again;
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if (i == j)
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break;
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}
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per_cpu(_cea_offset, i) = cea;
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}
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}
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#else /* !X86_64 */
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DECLARE_PER_CPU_PAGE_ALIGNED(struct doublefault_stack, doublefault_stack);
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static __always_inline unsigned int cea_offset(unsigned int cpu)
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{
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return cpu;
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}
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static inline void init_cea_offsets(void) { }
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#endif
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/* Is called from entry code, so must be noinstr */
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noinstr struct cpu_entry_area *get_cpu_entry_area(int cpu)
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{
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unsigned long va = CPU_ENTRY_AREA_PER_CPU + cea_offset(cpu) * CPU_ENTRY_AREA_SIZE;
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BUILD_BUG_ON(sizeof(struct cpu_entry_area) % PAGE_SIZE != 0);
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return (struct cpu_entry_area *) va;
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}
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EXPORT_SYMBOL(get_cpu_entry_area);
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void cea_set_pte(void *cea_vaddr, phys_addr_t pa, pgprot_t flags)
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{
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unsigned long va = (unsigned long) cea_vaddr;
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pte_t pte = pfn_pte(pa >> PAGE_SHIFT, flags);
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/*
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* The cpu_entry_area is shared between the user and kernel
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* page tables. All of its ptes can safely be global.
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* _PAGE_GLOBAL gets reused to help indicate PROT_NONE for
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* non-present PTEs, so be careful not to set it in that
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* case to avoid confusion.
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*/
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if (boot_cpu_has(X86_FEATURE_PGE) &&
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(pgprot_val(flags) & _PAGE_PRESENT))
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pte = pte_set_flags(pte, _PAGE_GLOBAL);
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set_pte_vaddr(va, pte);
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}
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static void __init
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cea_map_percpu_pages(void *cea_vaddr, void *ptr, int pages, pgprot_t prot)
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{
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for ( ; pages; pages--, cea_vaddr+= PAGE_SIZE, ptr += PAGE_SIZE)
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cea_set_pte(cea_vaddr, per_cpu_ptr_to_phys(ptr), prot);
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}
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static void __init percpu_setup_debug_store(unsigned int cpu)
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{
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#ifdef CONFIG_CPU_SUP_INTEL
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unsigned int npages;
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void *cea;
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if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
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return;
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cea = &get_cpu_entry_area(cpu)->cpu_debug_store;
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npages = sizeof(struct debug_store) / PAGE_SIZE;
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BUILD_BUG_ON(sizeof(struct debug_store) % PAGE_SIZE != 0);
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cea_map_percpu_pages(cea, &per_cpu(cpu_debug_store, cpu), npages,
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PAGE_KERNEL);
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cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers;
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/*
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* Force the population of PMDs for not yet allocated per cpu
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* memory like debug store buffers.
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*/
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npages = sizeof(struct debug_store_buffers) / PAGE_SIZE;
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for (; npages; npages--, cea += PAGE_SIZE)
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cea_set_pte(cea, 0, PAGE_NONE);
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#endif
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}
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#ifdef CONFIG_X86_64
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#define cea_map_stack(name) do { \
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npages = sizeof(estacks->name## _stack) / PAGE_SIZE; \
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cea_map_percpu_pages(cea->estacks.name## _stack, \
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estacks->name## _stack, npages, PAGE_KERNEL); \
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} while (0)
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static void __init percpu_setup_exception_stacks(unsigned int cpu)
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{
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struct exception_stacks *estacks = per_cpu_ptr(&exception_stacks, cpu);
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struct cpu_entry_area *cea = get_cpu_entry_area(cpu);
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unsigned int npages;
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BUILD_BUG_ON(sizeof(exception_stacks) % PAGE_SIZE != 0);
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per_cpu(cea_exception_stacks, cpu) = &cea->estacks;
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/*
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* The exceptions stack mappings in the per cpu area are protected
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* by guard pages so each stack must be mapped separately. DB2 is
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* not mapped; it just exists to catch triple nesting of #DB.
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*/
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cea_map_stack(DF);
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cea_map_stack(NMI);
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cea_map_stack(DB);
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cea_map_stack(MCE);
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if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) {
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if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) {
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cea_map_stack(VC);
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cea_map_stack(VC2);
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}
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}
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}
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#else
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static inline void percpu_setup_exception_stacks(unsigned int cpu)
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{
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struct cpu_entry_area *cea = get_cpu_entry_area(cpu);
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cea_map_percpu_pages(&cea->doublefault_stack,
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&per_cpu(doublefault_stack, cpu), 1, PAGE_KERNEL);
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}
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#endif
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/* Setup the fixmap mappings only once per-processor */
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static void __init setup_cpu_entry_area(unsigned int cpu)
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{
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struct cpu_entry_area *cea = get_cpu_entry_area(cpu);
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#ifdef CONFIG_X86_64
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/* On 64-bit systems, we use a read-only fixmap GDT and TSS. */
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pgprot_t gdt_prot = PAGE_KERNEL_RO;
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pgprot_t tss_prot = PAGE_KERNEL_RO;
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#else
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/*
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* On 32-bit systems, the GDT cannot be read-only because
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* our double fault handler uses a task gate, and entering through
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* a task gate needs to change an available TSS to busy. If the
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* GDT is read-only, that will triple fault. The TSS cannot be
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* read-only because the CPU writes to it on task switches.
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*/
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pgprot_t gdt_prot = PAGE_KERNEL;
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pgprot_t tss_prot = PAGE_KERNEL;
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#endif
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kasan_populate_shadow_for_vaddr(cea, CPU_ENTRY_AREA_SIZE,
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early_cpu_to_node(cpu));
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cea_set_pte(&cea->gdt, get_cpu_gdt_paddr(cpu), gdt_prot);
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cea_map_percpu_pages(&cea->entry_stack_page,
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per_cpu_ptr(&entry_stack_storage, cpu), 1,
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PAGE_KERNEL);
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/*
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* The Intel SDM says (Volume 3, 7.2.1):
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*
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* Avoid placing a page boundary in the part of the TSS that the
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* processor reads during a task switch (the first 104 bytes). The
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* processor may not correctly perform address translations if a
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* boundary occurs in this area. During a task switch, the processor
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* reads and writes into the first 104 bytes of each TSS (using
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* contiguous physical addresses beginning with the physical address
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* of the first byte of the TSS). So, after TSS access begins, if
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* part of the 104 bytes is not physically contiguous, the processor
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* will access incorrect information without generating a page-fault
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* exception.
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*
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* There are also a lot of errata involving the TSS spanning a page
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* boundary. Assert that we're not doing that.
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*/
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BUILD_BUG_ON((offsetof(struct tss_struct, x86_tss) ^
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offsetofend(struct tss_struct, x86_tss)) & PAGE_MASK);
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BUILD_BUG_ON(sizeof(struct tss_struct) % PAGE_SIZE != 0);
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/*
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* VMX changes the host TR limit to 0x67 after a VM exit. This is
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* okay, since 0x67 covers the size of struct x86_hw_tss. Make sure
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* that this is correct.
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*/
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BUILD_BUG_ON(offsetof(struct tss_struct, x86_tss) != 0);
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BUILD_BUG_ON(sizeof(struct x86_hw_tss) != 0x68);
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cea_map_percpu_pages(&cea->tss, &per_cpu(cpu_tss_rw, cpu),
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sizeof(struct tss_struct) / PAGE_SIZE, tss_prot);
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#ifdef CONFIG_X86_32
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per_cpu(cpu_entry_area, cpu) = cea;
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#endif
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percpu_setup_exception_stacks(cpu);
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percpu_setup_debug_store(cpu);
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}
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static __init void setup_cpu_entry_area_ptes(void)
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{
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#ifdef CONFIG_X86_32
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unsigned long start, end;
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/* The +1 is for the readonly IDT: */
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BUILD_BUG_ON((CPU_ENTRY_AREA_PAGES+1)*PAGE_SIZE != CPU_ENTRY_AREA_MAP_SIZE);
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BUG_ON(CPU_ENTRY_AREA_BASE & ~PMD_MASK);
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start = CPU_ENTRY_AREA_BASE;
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end = start + CPU_ENTRY_AREA_MAP_SIZE;
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/* Careful here: start + PMD_SIZE might wrap around */
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for (; start < end && start >= CPU_ENTRY_AREA_BASE; start += PMD_SIZE)
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populate_extra_pte(start);
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#endif
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}
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void __init setup_cpu_entry_areas(void)
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{
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unsigned int cpu;
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init_cea_offsets();
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setup_cpu_entry_area_ptes();
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for_each_possible_cpu(cpu)
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setup_cpu_entry_area(cpu);
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/*
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* This is the last essential update to swapper_pgdir which needs
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* to be synchronized to initial_page_table on 32bit.
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*/
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sync_initial_page_table();
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}
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