2023-08-30 17:31:07 +02:00
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/*
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* Freescale iMX PATA driver
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*
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* Copyright (C) 2011 Arnaud Patard <arnaud.patard@rtp-net.org>
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*
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* Based on pata_platform - Copyright (C) 2006 - 2007 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* TODO:
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* - dmaengine support
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*/
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#include <linux/ata.h>
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#include <linux/clk.h>
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#include <linux/libata.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#define DRV_NAME "pata_imx"
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#define PATA_IMX_ATA_TIME_OFF 0x00
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#define PATA_IMX_ATA_TIME_ON 0x01
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#define PATA_IMX_ATA_TIME_1 0x02
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#define PATA_IMX_ATA_TIME_2W 0x03
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#define PATA_IMX_ATA_TIME_2R 0x04
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#define PATA_IMX_ATA_TIME_AX 0x05
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#define PATA_IMX_ATA_TIME_PIO_RDX 0x06
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#define PATA_IMX_ATA_TIME_4 0x07
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#define PATA_IMX_ATA_TIME_9 0x08
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#define PATA_IMX_ATA_CONTROL 0x24
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#define PATA_IMX_ATA_CTRL_FIFO_RST_B (1<<7)
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#define PATA_IMX_ATA_CTRL_ATA_RST_B (1<<6)
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#define PATA_IMX_ATA_CTRL_IORDY_EN (1<<0)
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#define PATA_IMX_ATA_INT_EN 0x2C
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#define PATA_IMX_ATA_INTR_ATA_INTRQ2 (1<<3)
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#define PATA_IMX_DRIVE_DATA 0xA0
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#define PATA_IMX_DRIVE_CONTROL 0xD8
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static u32 pio_t4[] = { 30, 20, 15, 10, 10 };
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static u32 pio_t9[] = { 20, 15, 10, 10, 10 };
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static u32 pio_tA[] = { 35, 35, 35, 35, 35 };
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struct pata_imx_priv {
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struct clk *clk;
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/* timings/interrupt/control regs */
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void __iomem *host_regs;
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u32 ata_ctl;
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};
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static void pata_imx_set_timing(struct ata_device *adev,
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struct pata_imx_priv *priv)
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{
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struct ata_timing timing;
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unsigned long clkrate;
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u32 T, mode;
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clkrate = clk_get_rate(priv->clk);
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if (adev->pio_mode < XFER_PIO_0 || adev->pio_mode > XFER_PIO_4 ||
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!clkrate)
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return;
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T = 1000000000 / clkrate;
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ata_timing_compute(adev, adev->pio_mode, &timing, T * 1000, 0);
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mode = adev->pio_mode - XFER_PIO_0;
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writeb(3, priv->host_regs + PATA_IMX_ATA_TIME_OFF);
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writeb(3, priv->host_regs + PATA_IMX_ATA_TIME_ON);
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writeb(timing.setup, priv->host_regs + PATA_IMX_ATA_TIME_1);
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writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2W);
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writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2R);
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writeb(1, priv->host_regs + PATA_IMX_ATA_TIME_PIO_RDX);
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writeb(pio_t4[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_4);
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writeb(pio_t9[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_9);
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writeb(pio_tA[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_AX);
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}
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static void pata_imx_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pata_imx_priv *priv = ap->host->private_data;
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u32 val;
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pata_imx_set_timing(adev, priv);
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val = __raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL);
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if (ata_pio_need_iordy(adev))
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val |= PATA_IMX_ATA_CTRL_IORDY_EN;
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else
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val &= ~PATA_IMX_ATA_CTRL_IORDY_EN;
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__raw_writel(val, priv->host_regs + PATA_IMX_ATA_CONTROL);
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}
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2023-10-24 12:59:35 +02:00
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static const struct scsi_host_template pata_imx_sht = {
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2023-08-30 17:31:07 +02:00
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ATA_PIO_SHT(DRV_NAME),
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};
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static struct ata_port_operations pata_imx_port_ops = {
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.inherits = &ata_sff_port_ops,
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.sff_data_xfer = ata_sff_data_xfer32,
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.cable_detect = ata_cable_unknown,
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.set_piomode = pata_imx_set_piomode,
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};
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static void pata_imx_setup_port(struct ata_ioports *ioaddr)
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{
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/* Fixup the port shift for platforms that need it */
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ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2);
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ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2);
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ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
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ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2);
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ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);
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ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2);
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ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2);
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ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2);
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ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2);
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ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2);
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}
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static int pata_imx_probe(struct platform_device *pdev)
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{
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struct ata_host *host;
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struct ata_port *ap;
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struct pata_imx_priv *priv;
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int irq = 0;
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struct resource *io_res;
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int ret;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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priv = devm_kzalloc(&pdev->dev,
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sizeof(struct pata_imx_priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(priv->clk)) {
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dev_err(&pdev->dev, "Failed to get clock\n");
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return PTR_ERR(priv->clk);
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}
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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return ret;
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host = ata_host_alloc(&pdev->dev, 1);
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if (!host) {
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ret = -ENOMEM;
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goto err;
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}
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host->private_data = priv;
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ap = host->ports[0];
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ap->ops = &pata_imx_port_ops;
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ap->pio_mask = ATA_PIO4;
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ap->flags |= ATA_FLAG_SLAVE_POSS;
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io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->host_regs = devm_ioremap_resource(&pdev->dev, io_res);
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if (IS_ERR(priv->host_regs)) {
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ret = PTR_ERR(priv->host_regs);
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goto err;
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}
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ap->ioaddr.cmd_addr = priv->host_regs + PATA_IMX_DRIVE_DATA;
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ap->ioaddr.ctl_addr = priv->host_regs + PATA_IMX_DRIVE_CONTROL;
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ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
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pata_imx_setup_port(&ap->ioaddr);
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ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
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(unsigned long long)io_res->start + PATA_IMX_DRIVE_DATA,
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(unsigned long long)io_res->start + PATA_IMX_DRIVE_CONTROL);
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/* deassert resets */
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__raw_writel(PATA_IMX_ATA_CTRL_FIFO_RST_B |
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PATA_IMX_ATA_CTRL_ATA_RST_B,
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priv->host_regs + PATA_IMX_ATA_CONTROL);
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/* enable interrupts */
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__raw_writel(PATA_IMX_ATA_INTR_ATA_INTRQ2,
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priv->host_regs + PATA_IMX_ATA_INT_EN);
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/* activate */
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ret = ata_host_activate(host, irq, ata_sff_interrupt, 0,
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&pata_imx_sht);
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if (ret)
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goto err;
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return 0;
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err:
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clk_disable_unprepare(priv->clk);
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return ret;
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}
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static int pata_imx_remove(struct platform_device *pdev)
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{
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struct ata_host *host = platform_get_drvdata(pdev);
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struct pata_imx_priv *priv = host->private_data;
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ata_host_detach(host);
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__raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN);
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clk_disable_unprepare(priv->clk);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int pata_imx_suspend(struct device *dev)
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{
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struct ata_host *host = dev_get_drvdata(dev);
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struct pata_imx_priv *priv = host->private_data;
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ata_host_suspend(host, PMSG_SUSPEND);
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__raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN);
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priv->ata_ctl = __raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL);
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clk_disable_unprepare(priv->clk);
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return 0;
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}
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static int pata_imx_resume(struct device *dev)
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{
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struct ata_host *host = dev_get_drvdata(dev);
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struct pata_imx_priv *priv = host->private_data;
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int ret = clk_prepare_enable(priv->clk);
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if (ret)
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return ret;
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__raw_writel(priv->ata_ctl, priv->host_regs + PATA_IMX_ATA_CONTROL);
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__raw_writel(PATA_IMX_ATA_INTR_ATA_INTRQ2,
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priv->host_regs + PATA_IMX_ATA_INT_EN);
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ata_host_resume(host);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(pata_imx_pm_ops, pata_imx_suspend, pata_imx_resume);
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static const struct of_device_id imx_pata_dt_ids[] = {
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{
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.compatible = "fsl,imx27-pata",
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}, {
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/* sentinel */
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}
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};
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MODULE_DEVICE_TABLE(of, imx_pata_dt_ids);
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static struct platform_driver pata_imx_driver = {
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.probe = pata_imx_probe,
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.remove = pata_imx_remove,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = imx_pata_dt_ids,
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.pm = &pata_imx_pm_ops,
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},
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};
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module_platform_driver(pata_imx_driver);
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MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
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MODULE_DESCRIPTION("low-level driver for iMX PATA");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:" DRV_NAME);
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