2023-10-24 12:59:35 +02:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* (c) 1997-1998 Grant R. Guenther <grant@torque.net>
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*
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* on26.c is a low-level protocol driver for the
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* OnSpec 90c26 parallel to IDE adapter chip.
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*/
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2023-08-30 17:31:07 +02:00
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/wait.h>
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#include <asm/io.h>
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2023-10-24 12:59:35 +02:00
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#include "pata_parport.h"
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/*
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* mode codes: 0 nybble reads, 8-bit writes
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* 1 8-bit reads and writes
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* 2 8-bit EPP mode
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* 3 EPP-16
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* 4 EPP-32
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*/
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#define j44(a, b) (((a >> 4) & 0x0f) | (b & 0xf0))
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#define P1 \
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do { \
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w2(5); w2(0xd); w2(5); w2(0xd); w2(5); w2(4); \
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} while (0)
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#define P2 \
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do { \
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w2(5); w2(7); w2(5); w2(4); \
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} while (0)
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/*
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* cont = 0 - access the IDE register file
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* cont = 1 - access the IDE command set
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*/
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static int on26_read_regr(struct pi_adapter *pi, int cont, int regr)
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{
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int a, b, r;
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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r = (regr << 2) + 1 + cont;
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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switch (pi->mode) {
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case 0:
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w0(1); P1; w0(r); P2; w0(0); P1;
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2023-08-30 17:31:07 +02:00
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w2(6); a = r1(); w2(4);
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w2(6); b = r1(); w2(4);
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w2(6); w2(4); w2(6); w2(4);
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2023-10-24 12:59:35 +02:00
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return j44(a, b);
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case 1:
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w0(1); P1; w0(r); P2; w0(0); P1;
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2023-08-30 17:31:07 +02:00
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w2(0x26); a = r0(); w2(4); w2(0x26); w2(4);
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2023-10-24 12:59:35 +02:00
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return a;
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2023-08-30 17:31:07 +02:00
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case 2:
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case 3:
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2023-10-24 12:59:35 +02:00
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case 4:
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w3(1); w3(1); w2(5); w4(r); w2(4);
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2023-08-30 17:31:07 +02:00
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w3(0); w3(0); w2(0x24); a = r4(); w2(4);
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w2(0x24); (void)r4(); w2(4);
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2023-10-24 12:59:35 +02:00
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return a;
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}
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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return -1;
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}
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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static void on26_write_regr(struct pi_adapter *pi, int cont, int regr, int val)
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{
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int r = (regr << 2) + 1 + cont;
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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switch (pi->mode) {
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case 0:
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case 1:
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w0(1); P1; w0(r); P2; w0(0); P1;
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2023-08-30 17:31:07 +02:00
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w0(val); P2; w0(val); P2;
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break;
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case 2:
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case 3:
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2023-10-24 12:59:35 +02:00
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case 4:
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w3(1); w3(1); w2(5); w4(r); w2(4);
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w3(0); w3(0);
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2023-08-30 17:31:07 +02:00
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w2(5); w4(val); w2(4);
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w2(5); w4(val); w2(4);
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2023-10-24 12:59:35 +02:00
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break;
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}
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2023-08-30 17:31:07 +02:00
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}
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2023-10-24 12:59:35 +02:00
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#define CCP(x) \
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do { \
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w0(0xfe); w0(0xaa); w0(0x55); w0(0); \
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w0(0xff); w0(0x87); w0(0x78); w0(x); \
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w2(4); w2(5); w2(4); w0(0xff); \
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} while (0)
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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static void on26_connect(struct pi_adapter *pi)
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{
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int x;
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2023-08-30 17:31:07 +02:00
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pi->saved_r0 = r0();
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2023-10-24 12:59:35 +02:00
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pi->saved_r2 = r2();
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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CCP(0x20);
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if (pi->mode)
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x = 9;
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else
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x = 8;
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2023-08-30 17:31:07 +02:00
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w0(2); P1; w0(8); P2;
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w0(2); P1; w0(x); P2;
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}
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2023-10-24 12:59:35 +02:00
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static void on26_disconnect(struct pi_adapter *pi)
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{
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if (pi->mode >= 2) {
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w3(4); w3(4); w3(4); w3(4);
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} else {
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w0(4); P1; w0(4); P1;
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}
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2023-08-30 17:31:07 +02:00
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CCP(0x30);
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2023-10-24 12:59:35 +02:00
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w0(pi->saved_r0);
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w2(pi->saved_r2);
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}
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2023-08-30 17:31:07 +02:00
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#define RESET_WAIT 200
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2023-10-24 12:59:35 +02:00
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/* hard reset */
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static int on26_test_port(struct pi_adapter *pi)
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{
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int i, m, d, x = 0, y = 0;
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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pi->saved_r0 = r0();
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pi->saved_r2 = r2();
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d = pi->delay;
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m = pi->mode;
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pi->delay = 5;
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pi->mode = 0;
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w2(0xc);
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CCP(0x30); CCP(0);
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w0(0xfe); w0(0xaa); w0(0x55); w0(0); w0(0xff);
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i = ((r1() & 0xf0) << 4); w0(0x87);
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i |= (r1() & 0xf0); w0(0x78);
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w0(0x20); w2(4); w2(5);
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i |= ((r1() & 0xf0) >> 4);
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w2(4); w0(0xff);
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if (i == 0xb5f) {
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w0(2); P1; w0(0); P2;
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w0(3); P1; w0(0); P2;
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w0(2); P1; w0(8); P2; udelay(100);
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w0(2); P1; w0(0xa); P2; udelay(100);
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w0(2); P1; w0(8); P2; udelay(1000);
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on26_write_regr(pi, 0, 6, 0xa0);
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for (i = 0; i < RESET_WAIT; i++) {
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on26_write_regr(pi, 0, 6, 0xa0);
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x = on26_read_regr(pi, 0, 7);
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on26_write_regr(pi, 0, 6, 0xb0);
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y = on26_read_regr(pi, 0, 7);
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if (!((x & 0x80) || (y & 0x80)))
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break;
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mdelay(100);
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}
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if (i == RESET_WAIT)
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dev_err(&pi->dev,
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"on26: Device reset failed (%x,%x)\n", x, y);
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w0(4); P1; w0(4); P1;
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}
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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CCP(0x30);
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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pi->delay = d;
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pi->mode = m;
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w0(pi->saved_r0);
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w2(pi->saved_r2);
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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return 5;
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2023-08-30 17:31:07 +02:00
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}
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2023-10-24 12:59:35 +02:00
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static void on26_read_block(struct pi_adapter *pi, char *buf, int count)
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{
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int k, a, b;
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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switch (pi->mode) {
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case 0:
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w0(1); P1; w0(1); P2; w0(2); P1; w0(0x18); P2; w0(0); P1;
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2023-08-30 17:31:07 +02:00
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udelay(10);
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2023-10-24 12:59:35 +02:00
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for (k = 0; k < count; k++) {
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w2(6); a = r1();
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w2(4); b = r1();
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buf[k] = j44(a, b);
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}
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w0(2); P1; w0(8); P2;
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break;
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case 1:
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w0(1); P1; w0(1); P2; w0(2); P1; w0(0x19); P2; w0(0); P1;
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2023-08-30 17:31:07 +02:00
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udelay(10);
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2023-10-24 12:59:35 +02:00
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for (k = 0; k < count / 2; k++) {
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w2(0x26); buf[2 * k] = r0();
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w2(0x24); buf[2 * k + 1] = r0();
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}
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w0(2); P1; w0(9); P2;
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break;
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case 2:
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w3(1); w3(1); w2(5); w4(1); w2(4);
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2023-08-30 17:31:07 +02:00
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w3(0); w3(0); w2(0x24);
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udelay(10);
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2023-10-24 12:59:35 +02:00
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for (k = 0; k < count; k++)
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buf[k] = r4();
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w2(4);
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break;
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case 3:
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w3(1); w3(1); w2(5); w4(1); w2(4);
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w3(0); w3(0); w2(0x24);
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udelay(10);
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for (k = 0; k < count / 2; k++)
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((u16 *)buf)[k] = r4w();
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w2(4);
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break;
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case 4:
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w3(1); w3(1); w2(5); w4(1); w2(4);
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w3(0); w3(0); w2(0x24);
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udelay(10);
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for (k = 0; k < count / 4; k++)
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((u32 *)buf)[k] = r4l();
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w2(4);
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break;
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}
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2023-08-30 17:31:07 +02:00
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}
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2023-10-24 12:59:35 +02:00
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static void on26_write_block(struct pi_adapter *pi, char *buf, int count)
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{
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int k;
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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switch (pi->mode) {
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case 0:
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case 1:
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w0(1); P1; w0(1); P2;
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w0(2); P1; w0(0x18 + pi->mode); P2; w0(0); P1;
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2023-08-30 17:31:07 +02:00
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udelay(10);
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2023-10-24 12:59:35 +02:00
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for (k = 0; k < count / 2; k++) {
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w2(5); w0(buf[2 * k]);
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w2(7); w0(buf[2 * k + 1]);
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}
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w2(5); w2(4);
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w0(2); P1; w0(8 + pi->mode); P2;
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break;
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case 2:
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w3(1); w3(1); w2(5); w4(1); w2(4);
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2023-08-30 17:31:07 +02:00
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w3(0); w3(0); w2(0xc5);
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udelay(10);
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2023-10-24 12:59:35 +02:00
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for (k = 0; k < count; k++)
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w4(buf[k]);
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2023-08-30 17:31:07 +02:00
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w2(0xc4);
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2023-10-24 12:59:35 +02:00
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break;
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case 3:
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w3(1); w3(1); w2(5); w4(1); w2(4);
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w3(0); w3(0); w2(0xc5);
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udelay(10);
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for (k = 0; k < count / 2; k++)
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w4w(((u16 *)buf)[k]);
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w2(0xc4);
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break;
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case 4:
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w3(1); w3(1); w2(5); w4(1); w2(4);
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w3(0); w3(0); w2(0xc5);
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udelay(10);
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for (k = 0; k < count / 4; k++)
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w4l(((u32 *)buf)[k]);
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w2(0xc4);
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break;
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}
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2023-08-30 17:31:07 +02:00
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}
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2023-10-24 12:59:35 +02:00
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static void on26_log_adapter(struct pi_adapter *pi)
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{
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char *mode_string[5] = { "4-bit", "8-bit", "EPP-8", "EPP-16", "EPP-32" };
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2023-08-30 17:31:07 +02:00
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2023-10-24 12:59:35 +02:00
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dev_info(&pi->dev,
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"OnSpec 90c26 at 0x%x, mode %d (%s), delay %d\n",
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pi->port, pi->mode, mode_string[pi->mode], pi->delay);
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2023-08-30 17:31:07 +02:00
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}
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static struct pi_protocol on26 = {
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.owner = THIS_MODULE,
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.name = "on26",
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.max_mode = 5,
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.epp_first = 2,
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.default_delay = 1,
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.max_units = 1,
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.write_regr = on26_write_regr,
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.read_regr = on26_read_regr,
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.write_block = on26_write_block,
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.read_block = on26_read_block,
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.connect = on26_connect,
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.disconnect = on26_disconnect,
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.test_port = on26_test_port,
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.log_adapter = on26_log_adapter,
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};
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MODULE_LICENSE("GPL");
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2023-10-24 12:59:35 +02:00
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MODULE_AUTHOR("Grant R. Guenther <grant@torque.net>");
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MODULE_DESCRIPTION("Onspec 90c26 parallel port IDE adapter protocol driver");
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module_pata_parport_driver(on26);
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