405 lines
13 KiB
C
405 lines
13 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2022 Intel Corporation */
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#ifndef _ICP_QAT_FW_COMP_H_
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#define _ICP_QAT_FW_COMP_H_
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#include "icp_qat_fw.h"
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enum icp_qat_fw_comp_cmd_id {
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ICP_QAT_FW_COMP_CMD_STATIC = 0,
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ICP_QAT_FW_COMP_CMD_DYNAMIC = 1,
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ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2,
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ICP_QAT_FW_COMP_CMD_DELIMITER
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};
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enum icp_qat_fw_comp_20_cmd_id {
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ICP_QAT_FW_COMP_20_CMD_LZ4_COMPRESS = 3,
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ICP_QAT_FW_COMP_20_CMD_LZ4_DECOMPRESS = 4,
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ICP_QAT_FW_COMP_20_CMD_LZ4S_COMPRESS = 5,
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ICP_QAT_FW_COMP_20_CMD_LZ4S_DECOMPRESS = 6,
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ICP_QAT_FW_COMP_20_CMD_XP10_COMPRESS = 7,
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ICP_QAT_FW_COMP_20_CMD_XP10_DECOMPRESS = 8,
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ICP_QAT_FW_COMP_20_CMD_RESERVED_9 = 9,
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ICP_QAT_FW_COMP_23_CMD_ZSTD_COMPRESS = 10,
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ICP_QAT_FW_COMP_23_CMD_ZSTD_DECOMPRESS = 11,
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ICP_QAT_FW_COMP_20_CMD_DELIMITER
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};
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#define ICP_QAT_FW_COMP_STATELESS_SESSION 0
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#define ICP_QAT_FW_COMP_STATEFUL_SESSION 1
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#define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0
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#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1
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#define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0
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#define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1
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#define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0
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#define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1
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#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1
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#define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0
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#define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2
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#define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1
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#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3
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#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1
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#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4
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#define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1
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#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5
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#define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1
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#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7
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#define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1
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#define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \
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ret_uncomp, secure_ram) \
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((((sesstype) & ICP_QAT_FW_COMP_SESSION_TYPE_MASK) << \
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ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \
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(((autoselect) & ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) << \
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ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \
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(((enhanced_asb) & ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) << \
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ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \
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(((ret_uncomp) & ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) << \
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ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \
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(((secure_ram) & ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) << \
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ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS))
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#define ICP_QAT_FW_COMP_SESSION_TYPE_GET(flags) \
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QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS, \
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ICP_QAT_FW_COMP_SESSION_TYPE_MASK)
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#define ICP_QAT_FW_COMP_SESSION_TYPE_SET(flags, val) \
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QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS, \
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ICP_QAT_FW_COMP_SESSION_TYPE_MASK)
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#define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_GET(flags) \
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QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS, \
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ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK)
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#define ICP_QAT_FW_COMP_EN_ASB_GET(flags) \
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QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS, \
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ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK)
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#define ICP_QAT_FW_COMP_RET_UNCOMP_GET(flags) \
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QAT_FIELD_GET(flags, \
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ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS, \
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ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK)
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#define ICP_QAT_FW_COMP_SECURE_RAM_USE_GET(flags) \
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QAT_FIELD_GET(flags, \
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ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS, \
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ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK)
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struct icp_qat_fw_comp_req_hdr_cd_pars {
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union {
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struct {
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__u64 content_desc_addr;
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__u16 content_desc_resrvd1;
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__u8 content_desc_params_sz;
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__u8 content_desc_hdr_resrvd2;
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__u32 content_desc_resrvd3;
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} s;
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struct {
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__u32 comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2];
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__u32 content_desc_resrvd4;
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} sl;
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} u;
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};
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struct icp_qat_fw_comp_req_params {
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__u32 comp_len;
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__u32 out_buffer_sz;
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union {
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struct {
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__u32 initial_crc32;
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__u32 initial_adler;
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} legacy;
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__u64 crc_data_addr;
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} crc;
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__u32 req_par_flags;
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__u32 rsrvd;
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};
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#define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr, \
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cnvdfx, crc, xxhash_acc, \
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cnv_error_type, append_crc, \
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drop_data) \
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((((sop) & ICP_QAT_FW_COMP_SOP_MASK) << \
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ICP_QAT_FW_COMP_SOP_BITPOS) | \
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(((eop) & ICP_QAT_FW_COMP_EOP_MASK) << \
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ICP_QAT_FW_COMP_EOP_BITPOS) | \
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(((bfinal) & ICP_QAT_FW_COMP_BFINAL_MASK) \
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<< ICP_QAT_FW_COMP_BFINAL_BITPOS) | \
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(((cnv) & ICP_QAT_FW_COMP_CNV_MASK) << \
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ICP_QAT_FW_COMP_CNV_BITPOS) | \
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(((cnvnr) & ICP_QAT_FW_COMP_CNVNR_MASK) \
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<< ICP_QAT_FW_COMP_CNVNR_BITPOS) | \
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(((cnvdfx) & ICP_QAT_FW_COMP_CNV_DFX_MASK) \
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<< ICP_QAT_FW_COMP_CNV_DFX_BITPOS) | \
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(((crc) & ICP_QAT_FW_COMP_CRC_MODE_MASK) \
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<< ICP_QAT_FW_COMP_CRC_MODE_BITPOS) | \
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(((xxhash_acc) & ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK) \
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<< ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS) | \
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(((cnv_error_type) & ICP_QAT_FW_COMP_CNV_ERROR_MASK) \
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<< ICP_QAT_FW_COMP_CNV_ERROR_BITPOS) | \
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(((append_crc) & ICP_QAT_FW_COMP_APPEND_CRC_MASK) \
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<< ICP_QAT_FW_COMP_APPEND_CRC_BITPOS) | \
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(((drop_data) & ICP_QAT_FW_COMP_DROP_DATA_MASK) \
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<< ICP_QAT_FW_COMP_DROP_DATA_BITPOS))
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#define ICP_QAT_FW_COMP_NOT_SOP 0
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#define ICP_QAT_FW_COMP_SOP 1
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#define ICP_QAT_FW_COMP_NOT_EOP 0
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#define ICP_QAT_FW_COMP_EOP 1
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#define ICP_QAT_FW_COMP_NOT_BFINAL 0
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#define ICP_QAT_FW_COMP_BFINAL 1
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#define ICP_QAT_FW_COMP_NO_CNV 0
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#define ICP_QAT_FW_COMP_CNV 1
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#define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0
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#define ICP_QAT_FW_COMP_CNV_RECOVERY 1
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#define ICP_QAT_FW_COMP_NO_CNV_DFX 0
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#define ICP_QAT_FW_COMP_CNV_DFX 1
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#define ICP_QAT_FW_COMP_CRC_MODE_LEGACY 0
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#define ICP_QAT_FW_COMP_CRC_MODE_E2E 1
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#define ICP_QAT_FW_COMP_NO_XXHASH_ACC 0
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#define ICP_QAT_FW_COMP_XXHASH_ACC 1
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#define ICP_QAT_FW_COMP_APPEND_CRC 1
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#define ICP_QAT_FW_COMP_NO_APPEND_CRC 0
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#define ICP_QAT_FW_COMP_DROP_DATA 1
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#define ICP_QAT_FW_COMP_NO_DROP_DATA 0
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#define ICP_QAT_FW_COMP_SOP_BITPOS 0
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#define ICP_QAT_FW_COMP_SOP_MASK 0x1
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#define ICP_QAT_FW_COMP_EOP_BITPOS 1
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#define ICP_QAT_FW_COMP_EOP_MASK 0x1
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#define ICP_QAT_FW_COMP_BFINAL_BITPOS 6
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#define ICP_QAT_FW_COMP_BFINAL_MASK 0x1
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#define ICP_QAT_FW_COMP_CNV_BITPOS 16
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#define ICP_QAT_FW_COMP_CNV_MASK 0x1
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#define ICP_QAT_FW_COMP_CNVNR_BITPOS 17
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#define ICP_QAT_FW_COMP_CNVNR_MASK 0x1
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#define ICP_QAT_FW_COMP_CNV_DFX_BITPOS 18
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#define ICP_QAT_FW_COMP_CNV_DFX_MASK 0x1
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#define ICP_QAT_FW_COMP_CRC_MODE_BITPOS 19
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#define ICP_QAT_FW_COMP_CRC_MODE_MASK 0x1
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#define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS 20
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#define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK 0x1
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#define ICP_QAT_FW_COMP_CNV_ERROR_BITPOS 21
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#define ICP_QAT_FW_COMP_CNV_ERROR_MASK 0b111
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#define ICP_QAT_FW_COMP_CNV_ERROR_NONE 0b000
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#define ICP_QAT_FW_COMP_CNV_ERROR_CHECKSUM 0b001
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#define ICP_QAT_FW_COMP_CNV_ERROR_DCPR_OBC_DIFF 0b010
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#define ICP_QAT_FW_COMP_CNV_ERROR_DCPR 0b011
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#define ICP_QAT_FW_COMP_CNV_ERROR_XLT 0b100
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#define ICP_QAT_FW_COMP_CNV_ERROR_DCPR_IBC_DIFF 0b101
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#define ICP_QAT_FW_COMP_APPEND_CRC_BITPOS 24
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#define ICP_QAT_FW_COMP_APPEND_CRC_MASK 0x1
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#define ICP_QAT_FW_COMP_DROP_DATA_BITPOS 25
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#define ICP_QAT_FW_COMP_DROP_DATA_MASK 0x1
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#define ICP_QAT_FW_COMP_SOP_GET(flags) \
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QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_SOP_BITPOS, \
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ICP_QAT_FW_COMP_SOP_MASK)
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#define ICP_QAT_FW_COMP_SOP_SET(flags, val) \
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QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_SOP_BITPOS, \
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ICP_QAT_FW_COMP_SOP_MASK)
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#define ICP_QAT_FW_COMP_EOP_GET(flags) \
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QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_EOP_BITPOS, \
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ICP_QAT_FW_COMP_EOP_MASK)
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#define ICP_QAT_FW_COMP_EOP_SET(flags, val) \
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QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_EOP_BITPOS, \
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ICP_QAT_FW_COMP_EOP_MASK)
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#define ICP_QAT_FW_COMP_BFINAL_GET(flags) \
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QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_BFINAL_BITPOS, \
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ICP_QAT_FW_COMP_BFINAL_MASK)
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#define ICP_QAT_FW_COMP_BFINAL_SET(flags, val) \
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QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_BFINAL_BITPOS, \
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ICP_QAT_FW_COMP_BFINAL_MASK)
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#define ICP_QAT_FW_COMP_CNV_GET(flags) \
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QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNV_BITPOS, \
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ICP_QAT_FW_COMP_CNV_MASK)
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#define ICP_QAT_FW_COMP_CNVNR_GET(flags) \
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QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNVNR_BITPOS, \
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ICP_QAT_FW_COMP_CNVNR_MASK)
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#define ICP_QAT_FW_COMP_CNV_DFX_GET(flags) \
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QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNV_DFX_BITPOS, \
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ICP_QAT_FW_COMP_CNV_DFX_MASK)
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#define ICP_QAT_FW_COMP_CNV_DFX_SET(flags, val) \
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QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_CNV_DFX_BITPOS, \
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ICP_QAT_FW_COMP_CNV_DFX_MASK)
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#define ICP_QAT_FW_COMP_CRC_MODE_GET(flags) \
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QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CRC_MODE_BITPOS, \
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ICP_QAT_FW_COMP_CRC_MODE_MASK)
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#define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_GET(flags) \
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QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS, \
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ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK)
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#define ICP_QAT_FW_COMP_XXHASH_ACC_MODE_SET(flags, val) \
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QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS, \
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ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK)
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#define ICP_QAT_FW_COMP_CNV_ERROR_TYPE_GET(flags) \
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QAT_FIELD_GET(flags, ICP_QAT_FW_COMP_CNV_ERROR_BITPOS, \
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ICP_QAT_FW_COMP_CNV_ERROR_MASK)
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#define ICP_QAT_FW_COMP_CNV_ERROR_TYPE_SET(flags, val) \
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QAT_FIELD_SET(flags, val, ICP_QAT_FW_COMP_CNV_ERROR_BITPOS, \
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ICP_QAT_FW_COMP_CNV_ERROR_MASK)
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struct icp_qat_fw_xlt_req_params {
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__u64 inter_buff_ptr;
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};
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struct icp_qat_fw_comp_cd_hdr {
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__u16 ram_bank_flags;
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__u8 comp_cfg_offset;
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__u8 next_curr_id;
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__u32 resrvd;
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__u64 comp_state_addr;
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__u64 ram_banks_addr;
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};
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#define COMP_CPR_INITIAL_CRC 0
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#define COMP_CPR_INITIAL_ADLER 1
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struct icp_qat_fw_xlt_cd_hdr {
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__u16 resrvd1;
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__u8 resrvd2;
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__u8 next_curr_id;
|
||
|
|
__u32 resrvd3;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct icp_qat_fw_comp_req {
|
||
|
|
struct icp_qat_fw_comn_req_hdr comn_hdr;
|
||
|
|
struct icp_qat_fw_comp_req_hdr_cd_pars cd_pars;
|
||
|
|
struct icp_qat_fw_comn_req_mid comn_mid;
|
||
|
|
struct icp_qat_fw_comp_req_params comp_pars;
|
||
|
|
union {
|
||
|
|
struct icp_qat_fw_xlt_req_params xlt_pars;
|
||
|
|
__u32 resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2];
|
||
|
|
} u1;
|
||
|
|
__u32 resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2];
|
||
|
|
struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl;
|
||
|
|
union {
|
||
|
|
struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl;
|
||
|
|
__u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2];
|
||
|
|
} u2;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct icp_qat_fw_resp_comp_pars {
|
||
|
|
__u32 input_byte_counter;
|
||
|
|
__u32 output_byte_counter;
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
__u32 curr_crc32;
|
||
|
|
__u32 curr_adler_32;
|
||
|
|
} legacy;
|
||
|
|
__u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_2];
|
||
|
|
} crc;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct icp_qat_fw_comp_state {
|
||
|
|
__u32 rd8_counter;
|
||
|
|
__u32 status_flags;
|
||
|
|
__u32 in_counter;
|
||
|
|
__u32 out_counter;
|
||
|
|
__u64 intermediate_state;
|
||
|
|
__u32 lobc;
|
||
|
|
__u32 replaybc;
|
||
|
|
__u64 pcrc64_poly;
|
||
|
|
__u32 crc32;
|
||
|
|
__u32 adler_xxhash32;
|
||
|
|
__u64 pcrc64_xorout;
|
||
|
|
__u32 out_buf_size;
|
||
|
|
__u32 in_buf_size;
|
||
|
|
__u64 in_pcrc64;
|
||
|
|
__u64 out_pcrc64;
|
||
|
|
__u32 lobs;
|
||
|
|
__u32 libc;
|
||
|
|
__u64 reserved;
|
||
|
|
__u32 xxhash_state[4];
|
||
|
|
__u32 cleartext[4];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct icp_qat_fw_comp_resp {
|
||
|
|
struct icp_qat_fw_comn_resp_hdr comn_resp;
|
||
|
|
__u64 opaque_data;
|
||
|
|
struct icp_qat_fw_resp_comp_pars comp_resp_pars;
|
||
|
|
};
|
||
|
|
|
||
|
|
#define QAT_FW_COMP_BANK_FLAG_MASK 0x1
|
||
|
|
#define QAT_FW_COMP_BANK_I_BITPOS 8
|
||
|
|
#define QAT_FW_COMP_BANK_H_BITPOS 7
|
||
|
|
#define QAT_FW_COMP_BANK_G_BITPOS 6
|
||
|
|
#define QAT_FW_COMP_BANK_F_BITPOS 5
|
||
|
|
#define QAT_FW_COMP_BANK_E_BITPOS 4
|
||
|
|
#define QAT_FW_COMP_BANK_D_BITPOS 3
|
||
|
|
#define QAT_FW_COMP_BANK_C_BITPOS 2
|
||
|
|
#define QAT_FW_COMP_BANK_B_BITPOS 1
|
||
|
|
#define QAT_FW_COMP_BANK_A_BITPOS 0
|
||
|
|
|
||
|
|
enum icp_qat_fw_comp_bank_enabled {
|
||
|
|
ICP_QAT_FW_COMP_BANK_DISABLED = 0,
|
||
|
|
ICP_QAT_FW_COMP_BANK_ENABLED = 1,
|
||
|
|
ICP_QAT_FW_COMP_BANK_DELIMITER = 2
|
||
|
|
};
|
||
|
|
|
||
|
|
#define ICP_QAT_FW_COMP_RAM_FLAGS_BUILD(bank_i_enable, bank_h_enable, \
|
||
|
|
bank_g_enable, bank_f_enable, \
|
||
|
|
bank_e_enable, bank_d_enable, \
|
||
|
|
bank_c_enable, bank_b_enable, \
|
||
|
|
bank_a_enable) \
|
||
|
|
((((bank_i_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
|
||
|
|
QAT_FW_COMP_BANK_I_BITPOS) | \
|
||
|
|
(((bank_h_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
|
||
|
|
QAT_FW_COMP_BANK_H_BITPOS) | \
|
||
|
|
(((bank_g_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
|
||
|
|
QAT_FW_COMP_BANK_G_BITPOS) | \
|
||
|
|
(((bank_f_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
|
||
|
|
QAT_FW_COMP_BANK_F_BITPOS) | \
|
||
|
|
(((bank_e_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
|
||
|
|
QAT_FW_COMP_BANK_E_BITPOS) | \
|
||
|
|
(((bank_d_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
|
||
|
|
QAT_FW_COMP_BANK_D_BITPOS) | \
|
||
|
|
(((bank_c_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
|
||
|
|
QAT_FW_COMP_BANK_C_BITPOS) | \
|
||
|
|
(((bank_b_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
|
||
|
|
QAT_FW_COMP_BANK_B_BITPOS) | \
|
||
|
|
(((bank_a_enable) & QAT_FW_COMP_BANK_FLAG_MASK) << \
|
||
|
|
QAT_FW_COMP_BANK_A_BITPOS))
|
||
|
|
|
||
|
|
struct icp_qat_fw_comp_crc_data_struct {
|
||
|
|
__u32 crc32;
|
||
|
|
union {
|
||
|
|
__u32 adler;
|
||
|
|
__u32 xxhash;
|
||
|
|
} adler_xxhash_u;
|
||
|
|
__u32 cpr_in_crc_lo;
|
||
|
|
__u32 cpr_in_crc_hi;
|
||
|
|
__u32 cpr_out_crc_lo;
|
||
|
|
__u32 cpr_out_crc_hi;
|
||
|
|
__u32 xlt_in_crc_lo;
|
||
|
|
__u32 xlt_in_crc_hi;
|
||
|
|
__u32 xlt_out_crc_lo;
|
||
|
|
__u32 xlt_out_crc_hi;
|
||
|
|
__u32 prog_crc_poly_lo;
|
||
|
|
__u32 prog_crc_poly_hi;
|
||
|
|
__u32 xor_out_lo;
|
||
|
|
__u32 xor_out_hi;
|
||
|
|
__u32 append_crc_lo;
|
||
|
|
__u32 append_crc_hi;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct xxhash_acc_state_buff {
|
||
|
|
__u32 in_counter;
|
||
|
|
__u32 out_counter;
|
||
|
|
__u32 xxhash_state[4];
|
||
|
|
__u32 clear_txt[4];
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif
|