455 lines
12 KiB
C
455 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Crypto acceleration support for Rockchip RK3288
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*
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* Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
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*
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* Author: Zain Wang <zain.wang@rock-chips.com>
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*
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* Some ideas are from marvell/cesa.c and s5p-sss.c driver.
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*/
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#include <linux/device.h>
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#include <asm/unaligned.h>
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#include <linux/iopoll.h>
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#include "rk3288_crypto.h"
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/*
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* IC can not process zero message hash,
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* so we put the fixed hash out when met zero message.
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*/
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static bool rk_ahash_need_fallback(struct ahash_request *req)
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{
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struct scatterlist *sg;
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sg = req->src;
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while (sg) {
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if (!IS_ALIGNED(sg->offset, sizeof(u32))) {
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return true;
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}
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if (sg->length % 4) {
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return true;
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}
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sg = sg_next(sg);
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}
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return false;
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}
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static int rk_ahash_digest_fb(struct ahash_request *areq)
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{
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struct rk_ahash_rctx *rctx = ahash_request_ctx(areq);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
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struct rk_ahash_ctx *tfmctx = crypto_ahash_ctx(tfm);
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struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg);
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struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.hash);
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algt->stat_fb++;
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ahash_request_set_tfm(&rctx->fallback_req, tfmctx->fallback_tfm);
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rctx->fallback_req.base.flags = areq->base.flags &
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CRYPTO_TFM_REQ_MAY_SLEEP;
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rctx->fallback_req.nbytes = areq->nbytes;
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rctx->fallback_req.src = areq->src;
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rctx->fallback_req.result = areq->result;
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return crypto_ahash_digest(&rctx->fallback_req);
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}
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static int zero_message_process(struct ahash_request *req)
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{
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
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int rk_digest_size = crypto_ahash_digestsize(tfm);
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switch (rk_digest_size) {
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case SHA1_DIGEST_SIZE:
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memcpy(req->result, sha1_zero_message_hash, rk_digest_size);
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break;
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case SHA256_DIGEST_SIZE:
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memcpy(req->result, sha256_zero_message_hash, rk_digest_size);
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break;
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case MD5_DIGEST_SIZE:
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memcpy(req->result, md5_zero_message_hash, rk_digest_size);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void rk_ahash_reg_init(struct ahash_request *req,
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struct rk_crypto_info *dev)
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{
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struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
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int reg_status;
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reg_status = CRYPTO_READ(dev, RK_CRYPTO_CTRL) |
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RK_CRYPTO_HASH_FLUSH | _SBF(0xffff, 16);
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CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, reg_status);
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reg_status = CRYPTO_READ(dev, RK_CRYPTO_CTRL);
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reg_status &= (~RK_CRYPTO_HASH_FLUSH);
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reg_status |= _SBF(0xffff, 16);
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CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, reg_status);
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memset_io(dev->reg + RK_CRYPTO_HASH_DOUT_0, 0, 32);
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CRYPTO_WRITE(dev, RK_CRYPTO_INTENA, RK_CRYPTO_HRDMA_ERR_ENA |
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RK_CRYPTO_HRDMA_DONE_ENA);
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CRYPTO_WRITE(dev, RK_CRYPTO_INTSTS, RK_CRYPTO_HRDMA_ERR_INT |
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RK_CRYPTO_HRDMA_DONE_INT);
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CRYPTO_WRITE(dev, RK_CRYPTO_HASH_CTRL, rctx->mode |
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RK_CRYPTO_HASH_SWAP_DO);
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CRYPTO_WRITE(dev, RK_CRYPTO_CONF, RK_CRYPTO_BYTESWAP_HRFIFO |
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RK_CRYPTO_BYTESWAP_BRFIFO |
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RK_CRYPTO_BYTESWAP_BTFIFO);
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CRYPTO_WRITE(dev, RK_CRYPTO_HASH_MSG_LEN, req->nbytes);
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}
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static int rk_ahash_init(struct ahash_request *req)
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{
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struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
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struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
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ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
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rctx->fallback_req.base.flags = req->base.flags &
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CRYPTO_TFM_REQ_MAY_SLEEP;
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return crypto_ahash_init(&rctx->fallback_req);
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}
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static int rk_ahash_update(struct ahash_request *req)
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{
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struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
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struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
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ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
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rctx->fallback_req.base.flags = req->base.flags &
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CRYPTO_TFM_REQ_MAY_SLEEP;
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rctx->fallback_req.nbytes = req->nbytes;
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rctx->fallback_req.src = req->src;
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return crypto_ahash_update(&rctx->fallback_req);
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}
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static int rk_ahash_final(struct ahash_request *req)
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{
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struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
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struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
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ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
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rctx->fallback_req.base.flags = req->base.flags &
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CRYPTO_TFM_REQ_MAY_SLEEP;
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rctx->fallback_req.result = req->result;
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return crypto_ahash_final(&rctx->fallback_req);
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}
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static int rk_ahash_finup(struct ahash_request *req)
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{
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struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
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struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
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ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
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rctx->fallback_req.base.flags = req->base.flags &
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CRYPTO_TFM_REQ_MAY_SLEEP;
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rctx->fallback_req.nbytes = req->nbytes;
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rctx->fallback_req.src = req->src;
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rctx->fallback_req.result = req->result;
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return crypto_ahash_finup(&rctx->fallback_req);
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}
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static int rk_ahash_import(struct ahash_request *req, const void *in)
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{
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struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
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struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
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ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
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rctx->fallback_req.base.flags = req->base.flags &
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CRYPTO_TFM_REQ_MAY_SLEEP;
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return crypto_ahash_import(&rctx->fallback_req, in);
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}
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static int rk_ahash_export(struct ahash_request *req, void *out)
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{
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struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
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struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
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ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
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rctx->fallback_req.base.flags = req->base.flags &
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CRYPTO_TFM_REQ_MAY_SLEEP;
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return crypto_ahash_export(&rctx->fallback_req, out);
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}
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static int rk_ahash_digest(struct ahash_request *req)
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{
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struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
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struct rk_crypto_info *dev;
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struct crypto_engine *engine;
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if (rk_ahash_need_fallback(req))
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return rk_ahash_digest_fb(req);
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if (!req->nbytes)
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return zero_message_process(req);
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dev = get_rk_crypto();
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rctx->dev = dev;
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engine = dev->engine;
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return crypto_transfer_hash_request_to_engine(engine, req);
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}
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static void crypto_ahash_dma_start(struct rk_crypto_info *dev, struct scatterlist *sg)
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{
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CRYPTO_WRITE(dev, RK_CRYPTO_HRDMAS, sg_dma_address(sg));
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CRYPTO_WRITE(dev, RK_CRYPTO_HRDMAL, sg_dma_len(sg) / 4);
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CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, RK_CRYPTO_HASH_START |
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(RK_CRYPTO_HASH_START << 16));
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}
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static int rk_hash_prepare(struct crypto_engine *engine, void *breq)
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{
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struct ahash_request *areq = container_of(breq, struct ahash_request, base);
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struct rk_ahash_rctx *rctx = ahash_request_ctx(areq);
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struct rk_crypto_info *rkc = rctx->dev;
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int ret;
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ret = dma_map_sg(rkc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE);
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if (ret <= 0)
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return -EINVAL;
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rctx->nrsg = ret;
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return 0;
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}
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static int rk_hash_unprepare(struct crypto_engine *engine, void *breq)
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{
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struct ahash_request *areq = container_of(breq, struct ahash_request, base);
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struct rk_ahash_rctx *rctx = ahash_request_ctx(areq);
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struct rk_crypto_info *rkc = rctx->dev;
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dma_unmap_sg(rkc->dev, areq->src, rctx->nrsg, DMA_TO_DEVICE);
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return 0;
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}
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static int rk_hash_run(struct crypto_engine *engine, void *breq)
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{
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struct ahash_request *areq = container_of(breq, struct ahash_request, base);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
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struct rk_ahash_rctx *rctx = ahash_request_ctx(areq);
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struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg);
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struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.hash);
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struct scatterlist *sg = areq->src;
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struct rk_crypto_info *rkc = rctx->dev;
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int err = 0;
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int i;
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u32 v;
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err = pm_runtime_resume_and_get(rkc->dev);
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if (err)
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return err;
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rctx->mode = 0;
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algt->stat_req++;
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rkc->nreq++;
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switch (crypto_ahash_digestsize(tfm)) {
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case SHA1_DIGEST_SIZE:
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rctx->mode = RK_CRYPTO_HASH_SHA1;
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break;
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case SHA256_DIGEST_SIZE:
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rctx->mode = RK_CRYPTO_HASH_SHA256;
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break;
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case MD5_DIGEST_SIZE:
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rctx->mode = RK_CRYPTO_HASH_MD5;
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break;
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default:
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err = -EINVAL;
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goto theend;
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}
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rk_ahash_reg_init(areq, rkc);
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while (sg) {
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reinit_completion(&rkc->complete);
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rkc->status = 0;
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crypto_ahash_dma_start(rkc, sg);
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wait_for_completion_interruptible_timeout(&rkc->complete,
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msecs_to_jiffies(2000));
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if (!rkc->status) {
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dev_err(rkc->dev, "DMA timeout\n");
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err = -EFAULT;
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goto theend;
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}
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sg = sg_next(sg);
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}
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/*
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* it will take some time to process date after last dma
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* transmission.
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*
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* waiting time is relative with the last date len,
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* so cannot set a fixed time here.
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* 10us makes system not call here frequently wasting
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* efficiency, and make it response quickly when dma
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* complete.
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*/
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readl_poll_timeout(rkc->reg + RK_CRYPTO_HASH_STS, v, v == 0, 10, 1000);
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for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++) {
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v = readl(rkc->reg + RK_CRYPTO_HASH_DOUT_0 + i * 4);
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put_unaligned_le32(v, areq->result + i * 4);
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}
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theend:
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pm_runtime_put_autosuspend(rkc->dev);
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local_bh_disable();
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crypto_finalize_hash_request(engine, breq, err);
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local_bh_enable();
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return 0;
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}
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static int rk_cra_hash_init(struct crypto_tfm *tfm)
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{
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struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm);
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const char *alg_name = crypto_tfm_alg_name(tfm);
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struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg);
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struct rk_crypto_tmp *algt = container_of(alg, struct rk_crypto_tmp, alg.hash);
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/* for fallback */
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tctx->fallback_tfm = crypto_alloc_ahash(alg_name, 0,
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CRYPTO_ALG_NEED_FALLBACK);
|
||
|
|
if (IS_ERR(tctx->fallback_tfm)) {
|
||
|
|
dev_err(algt->dev->dev, "Could not load fallback driver.\n");
|
||
|
|
return PTR_ERR(tctx->fallback_tfm);
|
||
|
|
}
|
||
|
|
|
||
|
|
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
||
|
|
sizeof(struct rk_ahash_rctx) +
|
||
|
|
crypto_ahash_reqsize(tctx->fallback_tfm));
|
||
|
|
|
||
|
|
tctx->enginectx.op.do_one_request = rk_hash_run;
|
||
|
|
tctx->enginectx.op.prepare_request = rk_hash_prepare;
|
||
|
|
tctx->enginectx.op.unprepare_request = rk_hash_unprepare;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void rk_cra_hash_exit(struct crypto_tfm *tfm)
|
||
|
|
{
|
||
|
|
struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm);
|
||
|
|
|
||
|
|
crypto_free_ahash(tctx->fallback_tfm);
|
||
|
|
}
|
||
|
|
|
||
|
|
struct rk_crypto_tmp rk_ahash_sha1 = {
|
||
|
|
.type = CRYPTO_ALG_TYPE_AHASH,
|
||
|
|
.alg.hash = {
|
||
|
|
.init = rk_ahash_init,
|
||
|
|
.update = rk_ahash_update,
|
||
|
|
.final = rk_ahash_final,
|
||
|
|
.finup = rk_ahash_finup,
|
||
|
|
.export = rk_ahash_export,
|
||
|
|
.import = rk_ahash_import,
|
||
|
|
.digest = rk_ahash_digest,
|
||
|
|
.halg = {
|
||
|
|
.digestsize = SHA1_DIGEST_SIZE,
|
||
|
|
.statesize = sizeof(struct sha1_state),
|
||
|
|
.base = {
|
||
|
|
.cra_name = "sha1",
|
||
|
|
.cra_driver_name = "rk-sha1",
|
||
|
|
.cra_priority = 300,
|
||
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
||
|
|
CRYPTO_ALG_NEED_FALLBACK,
|
||
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
||
|
|
.cra_ctxsize = sizeof(struct rk_ahash_ctx),
|
||
|
|
.cra_alignmask = 3,
|
||
|
|
.cra_init = rk_cra_hash_init,
|
||
|
|
.cra_exit = rk_cra_hash_exit,
|
||
|
|
.cra_module = THIS_MODULE,
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
struct rk_crypto_tmp rk_ahash_sha256 = {
|
||
|
|
.type = CRYPTO_ALG_TYPE_AHASH,
|
||
|
|
.alg.hash = {
|
||
|
|
.init = rk_ahash_init,
|
||
|
|
.update = rk_ahash_update,
|
||
|
|
.final = rk_ahash_final,
|
||
|
|
.finup = rk_ahash_finup,
|
||
|
|
.export = rk_ahash_export,
|
||
|
|
.import = rk_ahash_import,
|
||
|
|
.digest = rk_ahash_digest,
|
||
|
|
.halg = {
|
||
|
|
.digestsize = SHA256_DIGEST_SIZE,
|
||
|
|
.statesize = sizeof(struct sha256_state),
|
||
|
|
.base = {
|
||
|
|
.cra_name = "sha256",
|
||
|
|
.cra_driver_name = "rk-sha256",
|
||
|
|
.cra_priority = 300,
|
||
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
||
|
|
CRYPTO_ALG_NEED_FALLBACK,
|
||
|
|
.cra_blocksize = SHA256_BLOCK_SIZE,
|
||
|
|
.cra_ctxsize = sizeof(struct rk_ahash_ctx),
|
||
|
|
.cra_alignmask = 3,
|
||
|
|
.cra_init = rk_cra_hash_init,
|
||
|
|
.cra_exit = rk_cra_hash_exit,
|
||
|
|
.cra_module = THIS_MODULE,
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
struct rk_crypto_tmp rk_ahash_md5 = {
|
||
|
|
.type = CRYPTO_ALG_TYPE_AHASH,
|
||
|
|
.alg.hash = {
|
||
|
|
.init = rk_ahash_init,
|
||
|
|
.update = rk_ahash_update,
|
||
|
|
.final = rk_ahash_final,
|
||
|
|
.finup = rk_ahash_finup,
|
||
|
|
.export = rk_ahash_export,
|
||
|
|
.import = rk_ahash_import,
|
||
|
|
.digest = rk_ahash_digest,
|
||
|
|
.halg = {
|
||
|
|
.digestsize = MD5_DIGEST_SIZE,
|
||
|
|
.statesize = sizeof(struct md5_state),
|
||
|
|
.base = {
|
||
|
|
.cra_name = "md5",
|
||
|
|
.cra_driver_name = "rk-md5",
|
||
|
|
.cra_priority = 300,
|
||
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
||
|
|
CRYPTO_ALG_NEED_FALLBACK,
|
||
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
||
|
|
.cra_ctxsize = sizeof(struct rk_ahash_ctx),
|
||
|
|
.cra_alignmask = 3,
|
||
|
|
.cra_init = rk_cra_hash_init,
|
||
|
|
.cra_exit = rk_cra_hash_exit,
|
||
|
|
.cra_module = THIS_MODULE,
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
};
|