413 lines
9.7 KiB
C
413 lines
9.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Microchip Polarfire FPGA programming over slave SPI interface.
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*/
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#include <asm/unaligned.h>
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#include <linux/delay.h>
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/spi/spi.h>
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#define MPF_SPI_ISC_ENABLE 0x0B
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#define MPF_SPI_ISC_DISABLE 0x0C
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#define MPF_SPI_READ_STATUS 0x00
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#define MPF_SPI_READ_DATA 0x01
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#define MPF_SPI_FRAME_INIT 0xAE
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#define MPF_SPI_FRAME 0xEE
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#define MPF_SPI_PRG_MODE 0x01
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#define MPF_SPI_RELEASE 0x23
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#define MPF_SPI_FRAME_SIZE 16
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#define MPF_HEADER_SIZE_OFFSET 24
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#define MPF_DATA_SIZE_OFFSET 55
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#define MPF_LOOKUP_TABLE_RECORD_SIZE 9
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#define MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET 0
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#define MPF_LOOKUP_TABLE_BLOCK_START_OFFSET 1
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#define MPF_COMPONENTS_SIZE_ID 5
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#define MPF_BITSTREAM_ID 8
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#define MPF_BITS_PER_COMPONENT_SIZE 22
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#define MPF_STATUS_POLL_TIMEOUT (2 * USEC_PER_SEC)
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#define MPF_STATUS_BUSY BIT(0)
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#define MPF_STATUS_READY BIT(1)
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#define MPF_STATUS_SPI_VIOLATION BIT(2)
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#define MPF_STATUS_SPI_ERROR BIT(3)
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struct mpf_priv {
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struct spi_device *spi;
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bool program_mode;
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u8 tx __aligned(ARCH_KMALLOC_MINALIGN);
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u8 rx;
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};
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static int mpf_read_status(struct mpf_priv *priv)
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{
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/*
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* HW status is returned on MISO in the first byte after CS went
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* active. However, first reading can be inadequate, so we submit
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* two identical SPI transfers and use result of the later one.
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*/
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struct spi_transfer xfers[2] = {
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{
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.tx_buf = &priv->tx,
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.rx_buf = &priv->rx,
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.len = 1,
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.cs_change = 1,
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}, {
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.tx_buf = &priv->tx,
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.rx_buf = &priv->rx,
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.len = 1,
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},
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};
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u8 status;
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int ret;
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priv->tx = MPF_SPI_READ_STATUS;
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ret = spi_sync_transfer(priv->spi, xfers, 2);
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if (ret)
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return ret;
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status = priv->rx;
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if ((status & MPF_STATUS_SPI_VIOLATION) ||
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(status & MPF_STATUS_SPI_ERROR))
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return -EIO;
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return status;
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}
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static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr)
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{
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struct mpf_priv *priv = mgr->priv;
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bool program_mode;
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int status;
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program_mode = priv->program_mode;
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status = mpf_read_status(priv);
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if (!program_mode && !status)
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return FPGA_MGR_STATE_OPERATING;
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return FPGA_MGR_STATE_UNKNOWN;
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}
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static int mpf_ops_parse_header(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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size_t component_size_byte_num, component_size_byte_off,
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components_size_start, bitstream_start,
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block_id_offset, block_start_offset;
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u8 header_size, blocks_num, block_id;
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u32 block_start, component_size;
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u16 components_num, i;
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if (!buf) {
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dev_err(&mgr->dev, "Image buffer is not provided\n");
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return -EINVAL;
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}
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header_size = *(buf + MPF_HEADER_SIZE_OFFSET);
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if (header_size > count) {
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info->header_size = header_size;
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return -EAGAIN;
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}
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/*
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* Go through look-up table to find out where actual bitstream starts
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* and where sizes of components of the bitstream lies.
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*/
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blocks_num = *(buf + header_size - 1);
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block_id_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET;
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block_start_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_START_OFFSET;
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header_size += blocks_num * MPF_LOOKUP_TABLE_RECORD_SIZE;
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if (header_size > count) {
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info->header_size = header_size;
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return -EAGAIN;
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}
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components_size_start = 0;
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bitstream_start = 0;
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while (blocks_num--) {
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block_id = *(buf + block_id_offset);
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block_start = get_unaligned_le32(buf + block_start_offset);
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switch (block_id) {
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case MPF_BITSTREAM_ID:
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bitstream_start = block_start;
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info->header_size = block_start;
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if (block_start > count)
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return -EAGAIN;
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break;
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case MPF_COMPONENTS_SIZE_ID:
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components_size_start = block_start;
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break;
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default:
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break;
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}
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if (bitstream_start && components_size_start)
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break;
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block_id_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
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block_start_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
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}
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if (!bitstream_start || !components_size_start) {
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dev_err(&mgr->dev, "Failed to parse header look-up table\n");
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return -EFAULT;
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}
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/*
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* Parse bitstream size.
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* Sizes of components of the bitstream are 22-bits long placed next
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* to each other. Image header should be extended by now up to where
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* actual bitstream starts, so no need for overflow check anymore.
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*/
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components_num = get_unaligned_le16(buf + MPF_DATA_SIZE_OFFSET);
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for (i = 0; i < components_num; i++) {
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component_size_byte_num =
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(i * MPF_BITS_PER_COMPONENT_SIZE) / BITS_PER_BYTE;
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component_size_byte_off =
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(i * MPF_BITS_PER_COMPONENT_SIZE) % BITS_PER_BYTE;
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component_size = get_unaligned_le32(buf +
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components_size_start +
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component_size_byte_num);
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component_size >>= component_size_byte_off;
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component_size &= GENMASK(MPF_BITS_PER_COMPONENT_SIZE - 1, 0);
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info->data_size += component_size * MPF_SPI_FRAME_SIZE;
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}
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return 0;
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}
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static int mpf_poll_status(struct mpf_priv *priv, u8 mask)
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{
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int ret, status;
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/*
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* Busy poll HW status. Polling stops if any of the following
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* conditions are met:
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* - timeout is reached
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* - mpf_read_status() returns an error
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* - busy bit is cleared AND mask bits are set
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*/
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ret = read_poll_timeout(mpf_read_status, status,
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(status < 0) ||
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((status & (MPF_STATUS_BUSY | mask)) == mask),
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0, MPF_STATUS_POLL_TIMEOUT, false, priv);
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if (ret < 0)
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return ret;
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return status;
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}
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static int mpf_spi_write(struct mpf_priv *priv, const void *buf, size_t buf_size)
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{
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int status = mpf_poll_status(priv, 0);
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if (status < 0)
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return status;
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return spi_write_then_read(priv->spi, buf, buf_size, NULL, 0);
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}
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static int mpf_spi_write_then_read(struct mpf_priv *priv,
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const void *txbuf, size_t txbuf_size,
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void *rxbuf, size_t rxbuf_size)
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{
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const u8 read_command[] = { MPF_SPI_READ_DATA };
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int ret;
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ret = mpf_spi_write(priv, txbuf, txbuf_size);
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if (ret)
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return ret;
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ret = mpf_poll_status(priv, MPF_STATUS_READY);
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if (ret < 0)
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return ret;
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return spi_write_then_read(priv->spi, read_command, sizeof(read_command),
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rxbuf, rxbuf_size);
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}
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static int mpf_ops_write_init(struct fpga_manager *mgr,
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struct fpga_image_info *info, const char *buf,
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size_t count)
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{
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const u8 program_mode[] = { MPF_SPI_FRAME_INIT, MPF_SPI_PRG_MODE };
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const u8 isc_en_command[] = { MPF_SPI_ISC_ENABLE };
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struct mpf_priv *priv = mgr->priv;
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struct device *dev = &mgr->dev;
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u32 isc_ret = 0;
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int ret;
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if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
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dev_err(dev, "Partial reconfiguration is not supported\n");
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return -EOPNOTSUPP;
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}
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ret = mpf_spi_write_then_read(priv, isc_en_command, sizeof(isc_en_command),
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&isc_ret, sizeof(isc_ret));
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if (ret || isc_ret) {
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dev_err(dev, "Failed to enable ISC: spi_ret %d, isc_ret %u\n",
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ret, isc_ret);
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return -EFAULT;
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}
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ret = mpf_spi_write(priv, program_mode, sizeof(program_mode));
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if (ret) {
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dev_err(dev, "Failed to enter program mode: %d\n", ret);
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return ret;
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}
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priv->program_mode = true;
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return 0;
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}
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static int mpf_spi_frame_write(struct mpf_priv *priv, const char *buf)
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{
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struct spi_transfer xfers[2] = {
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{
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.tx_buf = &priv->tx,
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.len = 1,
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}, {
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.tx_buf = buf,
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.len = MPF_SPI_FRAME_SIZE,
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},
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};
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int ret;
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ret = mpf_poll_status(priv, 0);
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if (ret < 0)
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return ret;
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priv->tx = MPF_SPI_FRAME;
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return spi_sync_transfer(priv->spi, xfers, ARRAY_SIZE(xfers));
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}
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static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
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{
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struct mpf_priv *priv = mgr->priv;
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struct device *dev = &mgr->dev;
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int ret, i;
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if (count % MPF_SPI_FRAME_SIZE) {
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dev_err(dev, "Bitstream size is not a multiple of %d\n",
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MPF_SPI_FRAME_SIZE);
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return -EINVAL;
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}
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for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) {
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ret = mpf_spi_frame_write(priv, buf + i * MPF_SPI_FRAME_SIZE);
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if (ret) {
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dev_err(dev, "Failed to write bitstream frame %d/%zu\n",
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i, count / MPF_SPI_FRAME_SIZE);
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return ret;
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}
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}
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return 0;
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}
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static int mpf_ops_write_complete(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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const u8 isc_dis_command[] = { MPF_SPI_ISC_DISABLE };
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const u8 release_command[] = { MPF_SPI_RELEASE };
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struct mpf_priv *priv = mgr->priv;
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struct device *dev = &mgr->dev;
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int ret;
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ret = mpf_spi_write(priv, isc_dis_command, sizeof(isc_dis_command));
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if (ret) {
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dev_err(dev, "Failed to disable ISC: %d\n", ret);
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return ret;
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}
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usleep_range(1000, 2000);
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ret = mpf_spi_write(priv, release_command, sizeof(release_command));
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if (ret) {
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dev_err(dev, "Failed to exit program mode: %d\n", ret);
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return ret;
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}
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priv->program_mode = false;
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return 0;
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}
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static const struct fpga_manager_ops mpf_ops = {
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.state = mpf_ops_state,
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.initial_header_size = 71,
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.skip_header = true,
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.parse_header = mpf_ops_parse_header,
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.write_init = mpf_ops_write_init,
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.write = mpf_ops_write,
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.write_complete = mpf_ops_write_complete,
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};
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static int mpf_probe(struct spi_device *spi)
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{
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struct device *dev = &spi->dev;
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struct fpga_manager *mgr;
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struct mpf_priv *priv;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->spi = spi;
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|
|
mgr = devm_fpga_mgr_register(dev, "Microchip Polarfire SPI FPGA Manager",
|
||
|
|
&mpf_ops, priv);
|
||
|
|
|
||
|
|
return PTR_ERR_OR_ZERO(mgr);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct spi_device_id mpf_spi_ids[] = {
|
||
|
|
{ .name = "mpf-spi-fpga-mgr", },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(spi, mpf_spi_ids);
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_OF)
|
||
|
|
static const struct of_device_id mpf_of_ids[] = {
|
||
|
|
{ .compatible = "microchip,mpf-spi-fpga-mgr" },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, mpf_of_ids);
|
||
|
|
#endif /* IS_ENABLED(CONFIG_OF) */
|
||
|
|
|
||
|
|
static struct spi_driver mpf_driver = {
|
||
|
|
.probe = mpf_probe,
|
||
|
|
.id_table = mpf_spi_ids,
|
||
|
|
.driver = {
|
||
|
|
.name = "microchip_mpf_spi_fpga_mgr",
|
||
|
|
.of_match_table = of_match_ptr(mpf_of_ids),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
module_spi_driver(mpf_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("Microchip Polarfire SPI FPGA Manager");
|
||
|
|
MODULE_AUTHOR("Ivan Bornyakov <i.bornyakov@metrotek.ru>");
|
||
|
|
MODULE_LICENSE("GPL");
|