242 lines
8.3 KiB
C
242 lines
8.3 KiB
C
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/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu_eeprom.h"
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#include "amdgpu.h"
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/* AT24CM02 and M24M02-R have a 256-byte write page size.
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*/
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#define EEPROM_PAGE_BITS 8
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#define EEPROM_PAGE_SIZE (1U << EEPROM_PAGE_BITS)
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#define EEPROM_PAGE_MASK (EEPROM_PAGE_SIZE - 1)
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#define EEPROM_OFFSET_SIZE 2
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/* EEPROM memory addresses are 19-bits long, which can
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* be partitioned into 3, 8, 8 bits, for a total of 19.
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* The upper 3 bits are sent as part of the 7-bit
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* "Device Type Identifier"--an I2C concept, which for EEPROM devices
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* is hard-coded as 1010b, indicating that it is an EEPROM
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* device--this is the wire format, followed by the upper
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* 3 bits of the 19-bit address, followed by the direction,
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* followed by two bytes holding the rest of the 16-bits of
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* the EEPROM memory address. The format on the wire for EEPROM
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* devices is: 1010XYZD, A15:A8, A7:A0,
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* Where D is the direction and sequenced out by the hardware.
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* Bits XYZ are memory address bits 18, 17 and 16.
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* These bits are compared to how pins 1-3 of the part are connected,
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* depending on the size of the part, more on that later.
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*
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* Note that of this wire format, a client is in control
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* of, and needs to specify only XYZ, A15:A8, A7:0, bits,
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* which is exactly the EEPROM memory address, or offset,
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* in order to address up to 8 EEPROM devices on the I2C bus.
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*
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* For instance, a 2-Mbit I2C EEPROM part, addresses all its bytes,
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* using an 18-bit address, bit 17 to 0 and thus would use all but one bit of
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* the 19 bits previously mentioned. The designer would then not connect
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* pins 1 and 2, and pin 3 usually named "A_2" or "E2", would be connected to
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* either Vcc or GND. This would allow for up to two 2-Mbit parts on
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* the same bus, where one would be addressable with bit 18 as 1, and
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* the other with bit 18 of the address as 0.
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*
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* For a 2-Mbit part, bit 18 is usually known as the "Chip Enable" or
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* "Hardware Address Bit". This bit is compared to the load on pin 3
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* of the device, described above, and if there is a match, then this
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* device responds to the command. This way, you can connect two
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* 2-Mbit EEPROM devices on the same bus, but see one contiguous
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* memory from 0 to 7FFFFh, where address 0 to 3FFFF is in the device
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* whose pin 3 is connected to GND, and address 40000 to 7FFFFh is in
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* the 2nd device, whose pin 3 is connected to Vcc.
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*
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* This addressing you encode in the 32-bit "eeprom_addr" below,
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* namely the 19-bits "XYZ,A15:A0", as a single 19-bit address. For
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* instance, eeprom_addr = 0x6DA01, is 110_1101_1010_0000_0001, where
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* XYZ=110b, and A15:A0=DA01h. The XYZ bits become part of the device
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* address, and the rest of the address bits are sent as the memory
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* address bytes.
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*
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* That is, for an I2C EEPROM driver everything is controlled by
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* the "eeprom_addr".
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*
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* See also top of amdgpu_ras_eeprom.c.
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*
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* P.S. If you need to write, lock and read the Identification Page,
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* (M24M02-DR device only, which we do not use), change the "7" to
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* "0xF" in the macro below, and let the client set bit 20 to 1 in
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* "eeprom_addr", and set A10 to 0 to write into it, and A10 and A1 to
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* 1 to lock it permanently.
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*/
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#define MAKE_I2C_ADDR(_aa) ((0xA << 3) | (((_aa) >> 16) & 0xF))
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static int __amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,
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u8 *eeprom_buf, u16 buf_size, bool read)
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{
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u8 eeprom_offset_buf[EEPROM_OFFSET_SIZE];
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struct i2c_msg msgs[] = {
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{
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.flags = 0,
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.len = EEPROM_OFFSET_SIZE,
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.buf = eeprom_offset_buf,
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},
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{
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.flags = read ? I2C_M_RD : 0,
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},
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};
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const u8 *p = eeprom_buf;
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int r;
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u16 len;
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for (r = 0; buf_size > 0;
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buf_size -= len, eeprom_addr += len, eeprom_buf += len) {
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/* Set the EEPROM address we want to write to/read from.
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*/
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msgs[0].addr = MAKE_I2C_ADDR(eeprom_addr);
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msgs[1].addr = msgs[0].addr;
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msgs[0].buf[0] = (eeprom_addr >> 8) & 0xff;
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msgs[0].buf[1] = eeprom_addr & 0xff;
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if (!read) {
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/* Write the maximum amount of data, without
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* crossing the device's page boundary, as per
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* its spec. Partial page writes are allowed,
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* starting at any location within the page,
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* so long as the page boundary isn't crossed
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* over (actually the page pointer rolls
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* over).
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*
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* As per the AT24CM02 EEPROM spec, after
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* writing into a page, the I2C driver should
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* terminate the transfer, i.e. in
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* "i2c_transfer()" below, with a STOP
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* condition, so that the self-timed write
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* cycle begins. This is implied for the
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* "i2c_transfer()" abstraction.
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*/
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len = min(EEPROM_PAGE_SIZE - (eeprom_addr &
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EEPROM_PAGE_MASK),
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(u32)buf_size);
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} else {
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/* Reading from the EEPROM has no limitation
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* on the number of bytes read from the EEPROM
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* device--they are simply sequenced out.
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*/
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len = buf_size;
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}
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msgs[1].len = len;
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msgs[1].buf = eeprom_buf;
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/* This constitutes a START-STOP transaction.
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*/
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r = i2c_transfer(i2c_adap, msgs, ARRAY_SIZE(msgs));
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if (r != ARRAY_SIZE(msgs))
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break;
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if (!read) {
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/* According to EEPROM specs the length of the
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* self-writing cycle, tWR (tW), is 10 ms.
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*
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* TODO: Use polling on ACK, aka Acknowledge
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* Polling, to minimize waiting for the
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* internal write cycle to complete, as it is
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* usually smaller than tWR (tW).
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*/
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msleep(10);
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}
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}
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return r < 0 ? r : eeprom_buf - p;
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}
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/**
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* amdgpu_eeprom_xfer -- Read/write from/to an I2C EEPROM device
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* @i2c_adap: pointer to the I2C adapter to use
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* @eeprom_addr: EEPROM address from which to read/write
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* @eeprom_buf: pointer to data buffer to read into/write from
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* @buf_size: the size of @eeprom_buf
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* @read: True if reading from the EEPROM, false if writing
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*
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* Returns the number of bytes read/written; -errno on error.
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*/
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static int amdgpu_eeprom_xfer(struct i2c_adapter *i2c_adap, u32 eeprom_addr,
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u8 *eeprom_buf, u16 buf_size, bool read)
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{
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const struct i2c_adapter_quirks *quirks = i2c_adap->quirks;
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u16 limit;
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if (!quirks)
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limit = 0;
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else if (read)
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limit = quirks->max_read_len;
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else
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limit = quirks->max_write_len;
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if (limit == 0) {
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return __amdgpu_eeprom_xfer(i2c_adap, eeprom_addr,
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eeprom_buf, buf_size, read);
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} else if (limit <= EEPROM_OFFSET_SIZE) {
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dev_err_ratelimited(&i2c_adap->dev,
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"maddr:0x%04X size:0x%02X:quirk max_%s_len must be > %d",
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eeprom_addr, buf_size,
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read ? "read" : "write", EEPROM_OFFSET_SIZE);
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return -EINVAL;
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} else {
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u16 ps; /* Partial size */
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int res = 0, r;
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/* The "limit" includes all data bytes sent/received,
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* which would include the EEPROM_OFFSET_SIZE bytes.
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* Account for them here.
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*/
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limit -= EEPROM_OFFSET_SIZE;
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for ( ; buf_size > 0;
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buf_size -= ps, eeprom_addr += ps, eeprom_buf += ps) {
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ps = min(limit, buf_size);
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r = __amdgpu_eeprom_xfer(i2c_adap, eeprom_addr,
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eeprom_buf, ps, read);
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if (r < 0)
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return r;
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res += r;
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}
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return res;
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}
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}
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int amdgpu_eeprom_read(struct i2c_adapter *i2c_adap,
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u32 eeprom_addr, u8 *eeprom_buf,
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u16 bytes)
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{
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return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
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true);
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}
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int amdgpu_eeprom_write(struct i2c_adapter *i2c_adap,
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u32 eeprom_addr, u8 *eeprom_buf,
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u16 bytes)
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{
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return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
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false);
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}
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