2023-08-30 17:31:07 +02:00
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*
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*/
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#include <linux/kthread.h>
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#include <linux/wait.h>
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#include <linux/sched.h>
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#include <drm/drm_drv.h>
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#include "amdgpu.h"
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#include "amdgpu_trace.h"
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#include "amdgpu_reset.h"
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static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
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{
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struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
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struct amdgpu_job *job = to_amdgpu_job(s_job);
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struct amdgpu_task_info ti;
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struct amdgpu_device *adev = ring->adev;
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int idx;
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int r;
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if (!drm_dev_enter(adev_to_drm(adev), &idx)) {
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DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s",
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__func__, s_job->sched->name);
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/* Effectively the job is aborted as the device is gone */
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return DRM_GPU_SCHED_STAT_ENODEV;
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}
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memset(&ti, 0, sizeof(struct amdgpu_task_info));
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adev->job_hang = true;
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if (amdgpu_gpu_recovery &&
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amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
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DRM_ERROR("ring %s timeout, but soft recovered\n",
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s_job->sched->name);
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goto exit;
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}
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amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti);
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DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n",
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job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
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ring->fence_drv.sync_seq);
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DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n",
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ti.process_name, ti.tgid, ti.task_name, ti.pid);
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2023-10-24 12:59:35 +02:00
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dma_fence_set_error(&s_job->s_fence->finished, -ETIME);
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2023-08-30 17:31:07 +02:00
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if (amdgpu_device_should_recover_gpu(ring->adev)) {
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struct amdgpu_reset_context reset_context;
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memset(&reset_context, 0, sizeof(reset_context));
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reset_context.method = AMD_RESET_METHOD_NONE;
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reset_context.reset_req_dev = adev;
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clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
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r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context);
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if (r)
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DRM_ERROR("GPU Recovery Failed: %d\n", r);
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} else {
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drm_sched_suspend_timeout(&ring->sched);
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if (amdgpu_sriov_vf(adev))
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adev->virt.tdr_debug = true;
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}
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exit:
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adev->job_hang = false;
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drm_dev_exit(idx);
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return DRM_GPU_SCHED_STAT_NOMINAL;
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}
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int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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struct drm_sched_entity *entity, void *owner,
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unsigned int num_ibs, struct amdgpu_job **job)
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{
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if (num_ibs == 0)
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return -EINVAL;
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*job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL);
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if (!*job)
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return -ENOMEM;
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/*
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* Initialize the scheduler to at least some ring so that we always
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* have a pointer to adev.
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*/
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(*job)->base.sched = &adev->rings[0]->sched;
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(*job)->vm = vm;
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amdgpu_sync_create(&(*job)->explicit_sync);
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2023-10-24 12:59:35 +02:00
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(*job)->generation = amdgpu_vm_generation(adev, vm);
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2023-08-30 17:31:07 +02:00
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(*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET;
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if (!entity)
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return 0;
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return drm_sched_job_init(&(*job)->base, entity, owner);
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}
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int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,
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struct drm_sched_entity *entity, void *owner,
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size_t size, enum amdgpu_ib_pool_type pool_type,
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struct amdgpu_job **job)
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{
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int r;
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r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job);
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if (r)
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return r;
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(*job)->num_ibs = 1;
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r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]);
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if (r) {
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if (entity)
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drm_sched_job_cleanup(&(*job)->base);
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kfree(*job);
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}
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return r;
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}
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void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,
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struct amdgpu_bo *gws, struct amdgpu_bo *oa)
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{
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if (gds) {
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job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
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job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
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}
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if (gws) {
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job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
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job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
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}
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if (oa) {
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job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
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job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
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}
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}
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void amdgpu_job_free_resources(struct amdgpu_job *job)
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{
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struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched);
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struct dma_fence *f;
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unsigned i;
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/* Check if any fences where initialized */
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if (job->base.s_fence && job->base.s_fence->finished.ops)
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f = &job->base.s_fence->finished;
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else if (job->hw_fence.ops)
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f = &job->hw_fence;
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else
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f = NULL;
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for (i = 0; i < job->num_ibs; ++i)
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amdgpu_ib_free(ring->adev, &job->ibs[i], f);
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}
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static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
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{
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struct amdgpu_job *job = to_amdgpu_job(s_job);
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drm_sched_job_cleanup(s_job);
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amdgpu_sync_free(&job->explicit_sync);
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/* only put the hw fence if has embedded fence */
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if (!job->hw_fence.ops)
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kfree(job);
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else
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dma_fence_put(&job->hw_fence);
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}
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void amdgpu_job_set_gang_leader(struct amdgpu_job *job,
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struct amdgpu_job *leader)
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{
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struct dma_fence *fence = &leader->base.s_fence->scheduled;
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WARN_ON(job->gang_submit);
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/*
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* Don't add a reference when we are the gang leader to avoid circle
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* dependency.
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*/
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if (job != leader)
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dma_fence_get(fence);
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job->gang_submit = fence;
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}
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void amdgpu_job_free(struct amdgpu_job *job)
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{
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if (job->base.entity)
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drm_sched_job_cleanup(&job->base);
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amdgpu_job_free_resources(job);
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amdgpu_sync_free(&job->explicit_sync);
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if (job->gang_submit != &job->base.s_fence->scheduled)
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dma_fence_put(job->gang_submit);
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if (!job->hw_fence.ops)
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kfree(job);
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else
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dma_fence_put(&job->hw_fence);
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}
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struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job)
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{
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struct dma_fence *f;
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drm_sched_job_arm(&job->base);
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f = dma_fence_get(&job->base.s_fence->finished);
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amdgpu_job_free_resources(job);
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drm_sched_entity_push_job(&job->base);
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return f;
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}
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int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
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struct dma_fence **fence)
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{
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int r;
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job->base.sched = &ring->sched;
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r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence);
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if (r)
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return r;
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amdgpu_job_free(job);
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return 0;
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}
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static struct dma_fence *
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amdgpu_job_prepare_job(struct drm_sched_job *sched_job,
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struct drm_sched_entity *s_entity)
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{
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struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched);
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struct amdgpu_job *job = to_amdgpu_job(sched_job);
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struct dma_fence *fence = NULL;
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int r;
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2023-10-24 12:59:35 +02:00
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/* Ignore soft recovered fences here */
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r = drm_sched_entity_error(s_entity);
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if (r && r != -ENODATA)
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goto error;
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2023-08-30 17:31:07 +02:00
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if (!fence && job->gang_submit)
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fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit);
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while (!fence && job->vm && !job->vmid) {
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r = amdgpu_vmid_grab(job->vm, ring, job, &fence);
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2023-10-24 12:59:35 +02:00
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if (r) {
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2023-08-30 17:31:07 +02:00
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DRM_ERROR("Error getting VM ID (%d)\n", r);
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2023-10-24 12:59:35 +02:00
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goto error;
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}
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2023-08-30 17:31:07 +02:00
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}
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return fence;
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2023-10-24 12:59:35 +02:00
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error:
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dma_fence_set_error(&job->base.s_fence->finished, r);
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return NULL;
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2023-08-30 17:31:07 +02:00
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}
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static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
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{
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struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
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struct amdgpu_device *adev = ring->adev;
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struct dma_fence *fence = NULL, *finished;
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struct amdgpu_job *job;
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int r = 0;
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job = to_amdgpu_job(sched_job);
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finished = &job->base.s_fence->finished;
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trace_amdgpu_sched_run_job(job);
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/* Skip job if VRAM is lost and never resubmit gangs */
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2023-10-24 12:59:35 +02:00
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if (job->generation != amdgpu_vm_generation(adev, job->vm) ||
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2023-08-30 17:31:07 +02:00
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(job->job_run_counter && job->gang_submit))
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dma_fence_set_error(finished, -ECANCELED);
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if (finished->error < 0) {
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DRM_INFO("Skip scheduling IBs!\n");
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} else {
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r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
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&fence);
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if (r)
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DRM_ERROR("Error scheduling IBs (%d)\n", r);
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}
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job->job_run_counter++;
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amdgpu_job_free_resources(job);
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fence = r ? ERR_PTR(r) : fence;
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return fence;
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}
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#define to_drm_sched_job(sched_job) \
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container_of((sched_job), struct drm_sched_job, queue_node)
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void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)
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{
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struct drm_sched_job *s_job;
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struct drm_sched_entity *s_entity = NULL;
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int i;
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/* Signal all jobs not yet scheduled */
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for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) {
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struct drm_sched_rq *rq = &sched->sched_rq[i];
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spin_lock(&rq->lock);
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list_for_each_entry(s_entity, &rq->entities, list) {
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while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) {
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struct drm_sched_fence *s_fence = s_job->s_fence;
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dma_fence_signal(&s_fence->scheduled);
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dma_fence_set_error(&s_fence->finished, -EHWPOISON);
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dma_fence_signal(&s_fence->finished);
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}
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}
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spin_unlock(&rq->lock);
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}
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/* Signal all jobs already scheduled to HW */
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list_for_each_entry(s_job, &sched->pending_list, list) {
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struct drm_sched_fence *s_fence = s_job->s_fence;
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dma_fence_set_error(&s_fence->finished, -EHWPOISON);
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dma_fence_signal(&s_fence->finished);
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}
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}
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const struct drm_sched_backend_ops amdgpu_sched_ops = {
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.prepare_job = amdgpu_job_prepare_job,
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.run_job = amdgpu_job_run,
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.timedout_job = amdgpu_job_timedout,
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.free_job = amdgpu_job_free_cb
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};
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