2023-08-30 17:31:07 +02:00
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/*
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "amdgpu.h"
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#include "amdgpu_ras.h"
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2023-10-24 12:59:35 +02:00
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int amdgpu_nbio_ras_sw_init(struct amdgpu_device *adev)
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{
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int err;
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struct amdgpu_nbio_ras *ras;
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if (!adev->nbio.ras)
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return 0;
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ras = adev->nbio.ras;
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err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
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if (err) {
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dev_err(adev->dev, "Failed to register pcie_bif ras block!\n");
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return err;
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}
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strcpy(ras->ras_block.ras_comm.name, "pcie_bif");
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ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF;
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ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
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adev->nbio.ras_if = &ras->ras_block.ras_comm;
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return 0;
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}
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2023-08-30 17:31:07 +02:00
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int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
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{
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int r;
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r = amdgpu_ras_block_late_init(adev, ras_block);
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if (r)
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return r;
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if (amdgpu_ras_is_supported(adev, ras_block->block)) {
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r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
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if (r)
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goto late_fini;
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r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
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if (r)
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goto late_fini;
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}
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return 0;
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late_fini:
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amdgpu_ras_block_late_fini(adev, ras_block);
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return r;
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}
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