360 lines
11 KiB
C
360 lines
11 KiB
C
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "atom.h"
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#include "atombios_encoders.h"
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#include "amdgpu_pll.h"
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#include <asm/div64.h>
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#include <linux/gcd.h>
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/**
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* amdgpu_pll_reduce_ratio - fractional number reduction
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*
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* @nom: nominator
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* @den: denominator
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* @nom_min: minimum value for nominator
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* @den_min: minimum value for denominator
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*
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* Find the greatest common divisor and apply it on both nominator and
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* denominator, but make nominator and denominator are at least as large
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* as their minimum values.
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*/
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static void amdgpu_pll_reduce_ratio(unsigned *nom, unsigned *den,
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unsigned nom_min, unsigned den_min)
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{
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unsigned tmp;
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/* reduce the numbers to a simpler ratio */
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tmp = gcd(*nom, *den);
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*nom /= tmp;
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*den /= tmp;
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/* make sure nominator is large enough */
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if (*nom < nom_min) {
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tmp = DIV_ROUND_UP(nom_min, *nom);
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*nom *= tmp;
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*den *= tmp;
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}
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/* make sure the denominator is large enough */
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if (*den < den_min) {
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tmp = DIV_ROUND_UP(den_min, *den);
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*nom *= tmp;
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*den *= tmp;
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}
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}
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/**
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* amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
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*
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* @adev: amdgpu_device pointer
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* @nom: nominator
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* @den: denominator
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* @post_div: post divider
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* @fb_div_max: feedback divider maximum
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* @ref_div_max: reference divider maximum
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* @fb_div: resulting feedback divider
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* @ref_div: resulting reference divider
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*
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* Calculate feedback and reference divider for a given post divider. Makes
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* sure we stay within the limits.
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*/
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static void amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, unsigned int nom,
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unsigned int den, unsigned int post_div,
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unsigned int fb_div_max, unsigned int ref_div_max,
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unsigned int *fb_div, unsigned int *ref_div)
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{
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/* limit reference * post divider to a maximum */
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if (adev->family == AMDGPU_FAMILY_SI)
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ref_div_max = min(100 / post_div, ref_div_max);
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else
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ref_div_max = min(128 / post_div, ref_div_max);
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/* get matching reference and feedback divider */
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*ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
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*fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
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/* limit fb divider to its maximum */
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if (*fb_div > fb_div_max) {
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*ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
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*fb_div = fb_div_max;
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}
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}
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/**
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* amdgpu_pll_compute - compute PLL paramaters
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*
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* @adev: amdgpu_device pointer
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* @pll: information about the PLL
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* @freq: requested frequency
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* @dot_clock_p: resulting pixel clock
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* @fb_div_p: resulting feedback divider
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* @frac_fb_div_p: fractional part of the feedback divider
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* @ref_div_p: resulting reference divider
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* @post_div_p: resulting reference divider
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*
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* Try to calculate the PLL parameters to generate the given frequency:
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* dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
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*/
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void amdgpu_pll_compute(struct amdgpu_device *adev,
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struct amdgpu_pll *pll,
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u32 freq,
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u32 *dot_clock_p,
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u32 *fb_div_p,
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u32 *frac_fb_div_p,
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u32 *ref_div_p,
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u32 *post_div_p)
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{
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unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ?
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freq : freq / 10;
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unsigned fb_div_min, fb_div_max, fb_div;
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unsigned post_div_min, post_div_max, post_div;
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unsigned ref_div_min, ref_div_max, ref_div;
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unsigned post_div_best, diff_best;
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unsigned nom, den;
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/* determine allowed feedback divider range */
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fb_div_min = pll->min_feedback_div;
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fb_div_max = pll->max_feedback_div;
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if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
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fb_div_min *= 10;
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fb_div_max *= 10;
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}
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/* determine allowed ref divider range */
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if (pll->flags & AMDGPU_PLL_USE_REF_DIV)
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ref_div_min = pll->reference_div;
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else
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ref_div_min = pll->min_ref_div;
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if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV &&
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pll->flags & AMDGPU_PLL_USE_REF_DIV)
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ref_div_max = pll->reference_div;
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else
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ref_div_max = pll->max_ref_div;
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/* determine allowed post divider range */
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if (pll->flags & AMDGPU_PLL_USE_POST_DIV) {
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post_div_min = pll->post_div;
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post_div_max = pll->post_div;
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} else {
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unsigned vco_min, vco_max;
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if (pll->flags & AMDGPU_PLL_IS_LCD) {
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vco_min = pll->lcd_pll_out_min;
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vco_max = pll->lcd_pll_out_max;
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} else {
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vco_min = pll->pll_out_min;
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vco_max = pll->pll_out_max;
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}
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if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
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vco_min *= 10;
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vco_max *= 10;
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}
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post_div_min = vco_min / target_clock;
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if ((target_clock * post_div_min) < vco_min)
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++post_div_min;
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if (post_div_min < pll->min_post_div)
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post_div_min = pll->min_post_div;
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post_div_max = vco_max / target_clock;
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if ((target_clock * post_div_max) > vco_max)
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--post_div_max;
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if (post_div_max > pll->max_post_div)
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post_div_max = pll->max_post_div;
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}
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/* represent the searched ratio as fractional number */
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nom = target_clock;
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den = pll->reference_freq;
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/* reduce the numbers to a simpler ratio */
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amdgpu_pll_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
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/* now search for a post divider */
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if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP)
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post_div_best = post_div_min;
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else
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post_div_best = post_div_max;
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diff_best = ~0;
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for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
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unsigned diff;
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amdgpu_pll_get_fb_ref_div(adev, nom, den, post_div, fb_div_max,
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ref_div_max, &fb_div, &ref_div);
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diff = abs(target_clock - (pll->reference_freq * fb_div) /
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(ref_div * post_div));
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if (diff < diff_best || (diff == diff_best &&
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!(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) {
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post_div_best = post_div;
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diff_best = diff;
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}
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}
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post_div = post_div_best;
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/* get the feedback and reference divider for the optimal value */
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amdgpu_pll_get_fb_ref_div(adev, nom, den, post_div, fb_div_max, ref_div_max,
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&fb_div, &ref_div);
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/* reduce the numbers to a simpler ratio once more */
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/* this also makes sure that the reference divider is large enough */
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amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
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/* avoid high jitter with small fractional dividers */
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if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
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fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60);
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if (fb_div < fb_div_min) {
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unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
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fb_div *= tmp;
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ref_div *= tmp;
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}
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}
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/* and finally save the result */
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if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {
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*fb_div_p = fb_div / 10;
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*frac_fb_div_p = fb_div % 10;
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} else {
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*fb_div_p = fb_div;
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*frac_fb_div_p = 0;
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}
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*dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
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(pll->reference_freq * *frac_fb_div_p)) /
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(ref_div * post_div * 10);
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*ref_div_p = ref_div;
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*post_div_p = post_div;
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DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
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freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
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ref_div, post_div);
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}
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/**
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* amdgpu_pll_get_use_mask - look up a mask of which pplls are in use
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*
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* @crtc: drm crtc
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*
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* Returns the mask of which PPLLs (Pixel PLLs) are in use.
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*/
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u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_crtc *test_crtc;
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struct amdgpu_crtc *test_amdgpu_crtc;
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u32 pll_in_use = 0;
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list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
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if (crtc == test_crtc)
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continue;
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test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
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if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
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pll_in_use |= (1 << test_amdgpu_crtc->pll_id);
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}
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return pll_in_use;
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}
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/**
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* amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
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*
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* @crtc: drm crtc
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*
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* Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
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* also in DP mode. For DP, a single PPLL can be used for all DP
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* crtcs/encoders.
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*/
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int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_crtc *test_crtc;
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struct amdgpu_crtc *test_amdgpu_crtc;
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list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
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if (crtc == test_crtc)
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continue;
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test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
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if (test_amdgpu_crtc->encoder &&
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ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {
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/* for DP use the same PLL for all */
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if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
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return test_amdgpu_crtc->pll_id;
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}
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}
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return ATOM_PPLL_INVALID;
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}
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/**
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* amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
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*
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* @crtc: drm crtc
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*
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* Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
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* be shared (i.e., same clock).
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*/
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int amdgpu_pll_get_shared_nondp_ppll(struct drm_crtc *crtc)
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{
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struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_crtc *test_crtc;
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struct amdgpu_crtc *test_amdgpu_crtc;
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u32 adjusted_clock, test_adjusted_clock;
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adjusted_clock = amdgpu_crtc->adjusted_clock;
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if (adjusted_clock == 0)
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return ATOM_PPLL_INVALID;
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list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
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if (crtc == test_crtc)
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continue;
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test_amdgpu_crtc = to_amdgpu_crtc(test_crtc);
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if (test_amdgpu_crtc->encoder &&
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!ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {
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/* check if we are already driving this connector with another crtc */
|
||
|
|
if (test_amdgpu_crtc->connector == amdgpu_crtc->connector) {
|
||
|
|
/* if we are, return that pll */
|
||
|
|
if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
|
||
|
|
return test_amdgpu_crtc->pll_id;
|
||
|
|
}
|
||
|
|
/* for non-DP check the clock */
|
||
|
|
test_adjusted_clock = test_amdgpu_crtc->adjusted_clock;
|
||
|
|
if ((crtc->mode.clock == test_crtc->mode.clock) &&
|
||
|
|
(adjusted_clock == test_adjusted_clock) &&
|
||
|
|
(amdgpu_crtc->ss_enabled == test_amdgpu_crtc->ss_enabled) &&
|
||
|
|
(test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID))
|
||
|
|
return test_amdgpu_crtc->pll_id;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return ATOM_PPLL_INVALID;
|
||
|
|
}
|