2023-08-30 17:31:07 +02:00
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_RLC_H__
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#define __AMDGPU_RLC_H__
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#include "clearstate_defs.h"
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/* firmware ID used in rlc toc */
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typedef enum _FIRMWARE_ID_ {
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FIRMWARE_ID_INVALID = 0,
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FIRMWARE_ID_RLC_G_UCODE = 1,
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FIRMWARE_ID_RLC_TOC = 2,
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FIRMWARE_ID_RLCG_SCRATCH = 3,
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FIRMWARE_ID_RLC_SRM_ARAM = 4,
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FIRMWARE_ID_RLC_SRM_INDEX_ADDR = 5,
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FIRMWARE_ID_RLC_SRM_INDEX_DATA = 6,
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FIRMWARE_ID_RLC_P_UCODE = 7,
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FIRMWARE_ID_RLC_V_UCODE = 8,
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FIRMWARE_ID_RLX6_UCODE = 9,
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FIRMWARE_ID_RLX6_DRAM_BOOT = 10,
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FIRMWARE_ID_GLOBAL_TAP_DELAYS = 11,
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FIRMWARE_ID_SE0_TAP_DELAYS = 12,
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FIRMWARE_ID_SE1_TAP_DELAYS = 13,
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FIRMWARE_ID_GLOBAL_SE0_SE1_SKEW_DELAYS = 14,
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FIRMWARE_ID_SDMA0_UCODE = 15,
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FIRMWARE_ID_SDMA0_JT = 16,
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FIRMWARE_ID_SDMA1_UCODE = 17,
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FIRMWARE_ID_SDMA1_JT = 18,
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FIRMWARE_ID_CP_CE = 19,
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FIRMWARE_ID_CP_PFP = 20,
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FIRMWARE_ID_CP_ME = 21,
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FIRMWARE_ID_CP_MEC = 22,
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FIRMWARE_ID_CP_MES = 23,
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FIRMWARE_ID_MES_STACK = 24,
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FIRMWARE_ID_RLC_SRM_DRAM_SR = 25,
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FIRMWARE_ID_RLCG_SCRATCH_SR = 26,
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FIRMWARE_ID_RLCP_SCRATCH_SR = 27,
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FIRMWARE_ID_RLCV_SCRATCH_SR = 28,
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FIRMWARE_ID_RLX6_DRAM_SR = 29,
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FIRMWARE_ID_SDMA0_PG_CONTEXT = 30,
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FIRMWARE_ID_SDMA1_PG_CONTEXT = 31,
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FIRMWARE_ID_GLOBAL_MUX_SELECT_RAM = 32,
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FIRMWARE_ID_SE0_MUX_SELECT_RAM = 33,
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FIRMWARE_ID_SE1_MUX_SELECT_RAM = 34,
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FIRMWARE_ID_ACCUM_CTRL_RAM = 35,
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FIRMWARE_ID_RLCP_CAM = 36,
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FIRMWARE_ID_RLC_SPP_CAM_EXT = 37,
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FIRMWARE_ID_MAX = 38,
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} FIRMWARE_ID;
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typedef enum _SOC21_FIRMWARE_ID_ {
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SOC21_FIRMWARE_ID_INVALID = 0,
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SOC21_FIRMWARE_ID_RLC_G_UCODE = 1,
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SOC21_FIRMWARE_ID_RLC_TOC = 2,
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SOC21_FIRMWARE_ID_RLCG_SCRATCH = 3,
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SOC21_FIRMWARE_ID_RLC_SRM_ARAM = 4,
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SOC21_FIRMWARE_ID_RLC_P_UCODE = 5,
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SOC21_FIRMWARE_ID_RLC_V_UCODE = 6,
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SOC21_FIRMWARE_ID_RLX6_UCODE = 7,
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SOC21_FIRMWARE_ID_RLX6_UCODE_CORE1 = 8,
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SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT = 9,
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SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT_CORE1 = 10,
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SOC21_FIRMWARE_ID_SDMA_UCODE_TH0 = 11,
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SOC21_FIRMWARE_ID_SDMA_UCODE_TH1 = 12,
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SOC21_FIRMWARE_ID_CP_PFP = 13,
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SOC21_FIRMWARE_ID_CP_ME = 14,
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SOC21_FIRMWARE_ID_CP_MEC = 15,
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SOC21_FIRMWARE_ID_RS64_MES_P0 = 16,
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SOC21_FIRMWARE_ID_RS64_MES_P1 = 17,
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SOC21_FIRMWARE_ID_RS64_PFP = 18,
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SOC21_FIRMWARE_ID_RS64_ME = 19,
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SOC21_FIRMWARE_ID_RS64_MEC = 20,
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SOC21_FIRMWARE_ID_RS64_MES_P0_STACK = 21,
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SOC21_FIRMWARE_ID_RS64_MES_P1_STACK = 22,
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SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK = 23,
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SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK = 24,
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SOC21_FIRMWARE_ID_RS64_ME_P0_STACK = 25,
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SOC21_FIRMWARE_ID_RS64_ME_P1_STACK = 26,
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SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK = 27,
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SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK = 28,
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SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK = 29,
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SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK = 30,
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SOC21_FIRMWARE_ID_RLC_SRM_DRAM_SR = 31,
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SOC21_FIRMWARE_ID_RLCG_SCRATCH_SR = 32,
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SOC21_FIRMWARE_ID_RLCP_SCRATCH_SR = 33,
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SOC21_FIRMWARE_ID_RLCV_SCRATCH_SR = 34,
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SOC21_FIRMWARE_ID_RLX6_DRAM_SR = 35,
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SOC21_FIRMWARE_ID_RLX6_DRAM_SR_CORE1 = 36,
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SOC21_FIRMWARE_ID_MAX = 37
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} SOC21_FIRMWARE_ID;
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typedef struct _RLC_TABLE_OF_CONTENT {
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union {
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unsigned int DW0;
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struct {
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unsigned int offset : 25;
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unsigned int id : 7;
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};
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};
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union {
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unsigned int DW1;
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struct {
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unsigned int load_at_boot : 1;
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unsigned int load_at_vddgfx : 1;
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unsigned int load_at_reset : 1;
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unsigned int memory_destination : 2;
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unsigned int vfflr_image_code : 4;
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unsigned int load_mode_direct : 1;
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unsigned int save_for_vddgfx : 1;
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unsigned int save_for_vfflr : 1;
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unsigned int reserved : 1;
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unsigned int signed_source : 1;
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unsigned int size : 18;
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};
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};
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union {
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unsigned int DW2;
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struct {
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unsigned int indirect_addr_reg : 16;
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unsigned int index : 16;
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};
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};
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union {
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unsigned int DW3;
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struct {
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unsigned int indirect_data_reg : 16;
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unsigned int indirect_start_offset : 16;
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};
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};
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} RLC_TABLE_OF_CONTENT;
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#define RLC_TOC_MAX_SIZE 64
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struct amdgpu_rlc_funcs {
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bool (*is_rlc_enabled)(struct amdgpu_device *adev);
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2023-10-24 12:59:35 +02:00
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void (*set_safe_mode)(struct amdgpu_device *adev, int xcc_id);
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void (*unset_safe_mode)(struct amdgpu_device *adev, int xcc_id);
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2023-08-30 17:31:07 +02:00
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int (*init)(struct amdgpu_device *adev);
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u32 (*get_csb_size)(struct amdgpu_device *adev);
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void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer);
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int (*get_cp_table_num)(struct amdgpu_device *adev);
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int (*resume)(struct amdgpu_device *adev);
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void (*stop)(struct amdgpu_device *adev);
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void (*reset)(struct amdgpu_device *adev);
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void (*start)(struct amdgpu_device *adev);
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void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);
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bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
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};
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struct amdgpu_rlcg_reg_access_ctrl {
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uint32_t scratch_reg0;
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uint32_t scratch_reg1;
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uint32_t scratch_reg2;
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uint32_t scratch_reg3;
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uint32_t grbm_cntl;
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uint32_t grbm_idx;
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uint32_t spare_int;
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};
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struct amdgpu_rlc {
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/* for power gating */
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struct amdgpu_bo *save_restore_obj;
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uint64_t save_restore_gpu_addr;
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volatile uint32_t *sr_ptr;
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const u32 *reg_list;
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u32 reg_list_size;
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/* for clear state */
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struct amdgpu_bo *clear_state_obj;
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uint64_t clear_state_gpu_addr;
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volatile uint32_t *cs_ptr;
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const struct cs_section_def *cs_data;
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u32 clear_state_size;
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/* for cp tables */
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struct amdgpu_bo *cp_table_obj;
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uint64_t cp_table_gpu_addr;
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volatile uint32_t *cp_table_ptr;
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u32 cp_table_size;
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/* safe mode for updating CG/PG state */
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bool in_safe_mode[8];
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const struct amdgpu_rlc_funcs *funcs;
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/* for firmware data */
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u32 save_and_restore_offset;
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u32 clear_state_descriptor_offset;
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u32 avail_scratch_ram_locations;
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u32 reg_restore_list_size;
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u32 reg_list_format_start;
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u32 reg_list_format_separate_start;
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u32 starting_offsets_start;
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u32 reg_list_format_size_bytes;
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u32 reg_list_size_bytes;
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u32 reg_list_format_direct_reg_list_length;
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u32 save_restore_list_cntl_size_bytes;
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u32 save_restore_list_gpm_size_bytes;
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u32 save_restore_list_srm_size_bytes;
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u32 rlc_iram_ucode_size_bytes;
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u32 rlc_dram_ucode_size_bytes;
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u32 rlcp_ucode_size_bytes;
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u32 rlcv_ucode_size_bytes;
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u32 global_tap_delays_ucode_size_bytes;
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u32 se0_tap_delays_ucode_size_bytes;
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u32 se1_tap_delays_ucode_size_bytes;
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u32 se2_tap_delays_ucode_size_bytes;
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u32 se3_tap_delays_ucode_size_bytes;
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u32 *register_list_format;
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u32 *register_restore;
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u8 *save_restore_list_cntl;
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u8 *save_restore_list_gpm;
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u8 *save_restore_list_srm;
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u8 *rlc_iram_ucode;
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u8 *rlc_dram_ucode;
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u8 *rlcp_ucode;
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u8 *rlcv_ucode;
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u8 *global_tap_delays_ucode;
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u8 *se0_tap_delays_ucode;
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u8 *se1_tap_delays_ucode;
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u8 *se2_tap_delays_ucode;
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u8 *se3_tap_delays_ucode;
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bool is_rlc_v2_1;
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/* for rlc autoload */
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struct amdgpu_bo *rlc_autoload_bo;
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u64 rlc_autoload_gpu_addr;
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void *rlc_autoload_ptr;
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/* rlc toc buffer */
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struct amdgpu_bo *rlc_toc_bo;
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uint64_t rlc_toc_gpu_addr;
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void *rlc_toc_buf;
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bool rlcg_reg_access_supported;
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/* registers for rlcg indirect reg access */
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struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl;
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};
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2023-10-24 12:59:35 +02:00
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void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id);
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void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id);
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int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws);
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int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev);
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int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev);
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void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev);
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void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev);
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int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev,
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uint16_t version_major,
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uint16_t version_minor);
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#endif
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