454 lines
15 KiB
C
454 lines
15 KiB
C
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_atombios.h"
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#include "nbio_v7_9.h"
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#include "amdgpu_ras.h"
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#include "nbio/nbio_7_9_0_offset.h"
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#include "nbio/nbio_7_9_0_sh_mask.h"
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#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
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#include <uapi/linux/kfd_ioctl.h>
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#define NPS_MODE_MASK 0x000000FFL
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static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)
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{
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WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
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adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
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WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
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adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
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}
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static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev)
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{
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u32 tmp;
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tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
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tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, STRAP_ATI_REV_ID_DEV0_F0);
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return tmp;
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}
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static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable)
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{
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if (enable)
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
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BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
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else
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
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}
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static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev)
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{
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return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
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}
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static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
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bool use_doorbell, int doorbell_index, int doorbell_size)
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{
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u32 doorbell_range = 0, doorbell_ctrl = 0;
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int aid_id, dev_inst;
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dev_inst = GET_INST(SDMA0, instance);
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aid_id = adev->sdma.instance[instance].aid_id;
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if (use_doorbell == false)
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return;
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doorbell_range =
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REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
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BIF_DOORBELL0_RANGE_OFFSET_ENTRY, doorbell_index);
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doorbell_range =
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REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
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BIF_DOORBELL0_RANGE_SIZE_ENTRY, doorbell_size);
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doorbell_ctrl =
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REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_ENABLE, 1);
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doorbell_ctrl =
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REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_SIZE, doorbell_size);
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switch (dev_inst % adev->sdma.num_inst_per_aid) {
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case 0:
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WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1,
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4 * aid_id, doorbell_range);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWID, 0xe);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xe);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
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0x1);
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WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_1_CTRL,
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aid_id, doorbell_ctrl);
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break;
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case 1:
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WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2,
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4 * aid_id, doorbell_range);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWID, 0x8);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x8);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
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0x2);
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WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_2_CTRL,
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aid_id, doorbell_ctrl);
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break;
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case 2:
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WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3,
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4 * aid_id, doorbell_range);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWID, 0x9);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x9);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
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0x8);
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WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_5_CTRL,
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aid_id, doorbell_ctrl);
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break;
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case 3:
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WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4,
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4 * aid_id, doorbell_range);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWID, 0xa);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xa);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
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0x9);
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WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_6_CTRL,
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aid_id, doorbell_ctrl);
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break;
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default:
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break;
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}
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return;
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}
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static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
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int doorbell_index, int instance)
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{
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u32 doorbell_range = 0, doorbell_ctrl = 0;
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u32 aid_id = instance;
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if (use_doorbell) {
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doorbell_range = REG_SET_FIELD(doorbell_range,
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DOORBELL0_CTRL_ENTRY_0,
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BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
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doorbell_index);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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DOORBELL0_CTRL_ENTRY_0,
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BIF_DOORBELL0_RANGE_SIZE_ENTRY,
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0x9);
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if (aid_id)
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doorbell_range = REG_SET_FIELD(doorbell_range,
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DOORBELL0_CTRL_ENTRY_0,
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DOORBELL0_FENCE_ENABLE_ENTRY,
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0x4);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_ENABLE, 1);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWID, 0x4);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_SIZE, 0x9);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4);
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WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
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aid_id, doorbell_range);
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WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
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aid_id, doorbell_ctrl);
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} else {
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doorbell_range = REG_SET_FIELD(doorbell_range,
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DOORBELL0_CTRL_ENTRY_0,
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BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
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doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
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WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
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aid_id, doorbell_range);
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WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
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aid_id, doorbell_ctrl);
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}
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}
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static void nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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/* Enable to allow doorbell pass thru on pre-silicon bare-metal */
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WREG32_SOC15(NBIO, 0, regBIFC_DOORBELL_ACCESS_EN_PF, 0xfffff);
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WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,
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BIF_DOORBELL_APER_EN, enable ? 1 : 0);
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}
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static void nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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u32 tmp = 0;
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if (enable) {
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tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_EN, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_MODE, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_SIZE, 0);
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WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
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lower_32_bits(adev->doorbell.base));
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WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
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upper_32_bits(adev->doorbell.base));
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}
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WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
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}
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static void nbio_v7_9_ih_doorbell_range(struct amdgpu_device *adev,
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bool use_doorbell, int doorbell_index)
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{
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u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0;
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if (use_doorbell) {
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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DOORBELL0_CTRL_ENTRY_0,
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BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
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doorbell_index);
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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DOORBELL0_CTRL_ENTRY_0,
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BIF_DOORBELL0_RANGE_SIZE_ENTRY,
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0x8);
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ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_ENABLE, 1);
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ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWID, 0);
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ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_OFFSET, 0);
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ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_SIZE, 0x8);
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ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0);
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} else {
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
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DOORBELL0_CTRL_ENTRY_0,
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BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
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ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
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S2A_DOORBELL_ENTRY_1_CTRL,
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S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
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}
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WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0, ih_doorbell_range);
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WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, ih_doorbell_ctrl);
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}
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static void nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device *adev,
|
||
|
|
bool enable)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
static void nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device *adev,
|
||
|
|
bool enable)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
static void nbio_v7_9_get_clockgating_state(struct amdgpu_device *adev,
|
||
|
|
u64 *flags)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
static void nbio_v7_9_ih_control(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
u32 interrupt_cntl;
|
||
|
|
|
||
|
|
/* setup interrupt control */
|
||
|
|
WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
|
||
|
|
interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
|
||
|
|
/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
|
||
|
|
* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
|
||
|
|
*/
|
||
|
|
interrupt_cntl =
|
||
|
|
REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
|
||
|
|
/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
|
||
|
|
interrupt_cntl =
|
||
|
|
REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
|
||
|
|
WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
|
||
|
|
}
|
||
|
|
|
||
|
|
static u32 nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
|
||
|
|
}
|
||
|
|
|
||
|
|
static u32 nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
|
||
|
|
}
|
||
|
|
|
||
|
|
static u32 nbio_v7_9_get_pcie_index_offset(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
|
||
|
|
}
|
||
|
|
|
||
|
|
static u32 nbio_v7_9_get_pcie_data_offset(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
|
||
|
|
}
|
||
|
|
|
||
|
|
static u32 nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI);
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct nbio_hdp_flush_reg nbio_v7_9_hdp_flush_reg = {
|
||
|
|
.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
|
||
|
|
.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
|
||
|
|
.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
|
||
|
|
.ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
|
||
|
|
.ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
|
||
|
|
.ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
|
||
|
|
.ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
|
||
|
|
.ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
|
||
|
|
.ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
|
||
|
|
.ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
|
||
|
|
.ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
|
||
|
|
.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
|
||
|
|
.ref_and_mask_sdma2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
|
||
|
|
.ref_and_mask_sdma3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
|
||
|
|
.ref_and_mask_sdma4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
|
||
|
|
.ref_and_mask_sdma5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
|
||
|
|
.ref_and_mask_sdma6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
|
||
|
|
.ref_and_mask_sdma7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device *adev,
|
||
|
|
bool enable)
|
||
|
|
{
|
||
|
|
WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL,
|
||
|
|
DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
u32 tmp, px;
|
||
|
|
|
||
|
|
tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);
|
||
|
|
px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
|
||
|
|
PARTITION_MODE);
|
||
|
|
|
||
|
|
return px;
|
||
|
|
}
|
||
|
|
|
||
|
|
static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev,
|
||
|
|
u32 *supp_modes)
|
||
|
|
{
|
||
|
|
u32 tmp;
|
||
|
|
|
||
|
|
tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);
|
||
|
|
tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE);
|
||
|
|
|
||
|
|
if (supp_modes) {
|
||
|
|
*supp_modes =
|
||
|
|
RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ffs(tmp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void nbio_v7_9_init_registers(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
u32 inst_mask;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE,
|
||
|
|
0xff & ~(adev->gfx.xcc_mask));
|
||
|
|
|
||
|
|
WREG32_SOC15(NBIO, 0, regBIFC_GFX_INT_MONITOR_MASK, 0x7ff);
|
||
|
|
|
||
|
|
inst_mask = adev->aid_mask & ~1U;
|
||
|
|
for_each_inst(i, inst_mask) {
|
||
|
|
WREG32_SOC15_EXT(NBIO, i, regXCC_DOORBELL_FENCE, i,
|
||
|
|
XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK);
|
||
|
|
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
|
||
|
|
.get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset,
|
||
|
|
.get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset,
|
||
|
|
.get_pcie_index_offset = nbio_v7_9_get_pcie_index_offset,
|
||
|
|
.get_pcie_data_offset = nbio_v7_9_get_pcie_data_offset,
|
||
|
|
.get_pcie_index_hi_offset = nbio_v7_9_get_pcie_index_hi_offset,
|
||
|
|
.get_rev_id = nbio_v7_9_get_rev_id,
|
||
|
|
.mc_access_enable = nbio_v7_9_mc_access_enable,
|
||
|
|
.get_memsize = nbio_v7_9_get_memsize,
|
||
|
|
.sdma_doorbell_range = nbio_v7_9_sdma_doorbell_range,
|
||
|
|
.vcn_doorbell_range = nbio_v7_9_vcn_doorbell_range,
|
||
|
|
.enable_doorbell_aperture = nbio_v7_9_enable_doorbell_aperture,
|
||
|
|
.enable_doorbell_selfring_aperture = nbio_v7_9_enable_doorbell_selfring_aperture,
|
||
|
|
.ih_doorbell_range = nbio_v7_9_ih_doorbell_range,
|
||
|
|
.enable_doorbell_interrupt = nbio_v7_9_enable_doorbell_interrupt,
|
||
|
|
.update_medium_grain_clock_gating = nbio_v7_9_update_medium_grain_clock_gating,
|
||
|
|
.update_medium_grain_light_sleep = nbio_v7_9_update_medium_grain_light_sleep,
|
||
|
|
.get_clockgating_state = nbio_v7_9_get_clockgating_state,
|
||
|
|
.ih_control = nbio_v7_9_ih_control,
|
||
|
|
.remap_hdp_registers = nbio_v7_9_remap_hdp_registers,
|
||
|
|
.get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
|
||
|
|
.get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
|
||
|
|
.init_registers = nbio_v7_9_init_registers,
|
||
|
|
};
|