383 lines
11 KiB
C
383 lines
11 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Huang Rui
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*
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*/
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "amdgpu.h"
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#include "amdgpu_psp.h"
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#include "amdgpu_ucode.h"
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#include "soc15_common.h"
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#include "psp_v3_1.h"
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#include "mp/mp_9_0_offset.h"
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#include "mp/mp_9_0_sh_mask.h"
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#include "gc/gc_9_0_offset.h"
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#include "sdma0/sdma0_4_0_offset.h"
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#include "nbio/nbio_6_1_offset.h"
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#include "oss/osssys_4_0_offset.h"
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#include "oss/osssys_4_0_sh_mask.h"
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MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
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MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
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MODULE_FIRMWARE("amdgpu/vega10_cap.bin");
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MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
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MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
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#define smnMP1_FIRMWARE_FLAGS 0x3010028
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static int psp_v3_1_ring_stop(struct psp_context *psp,
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enum psp_ring_type ring_type);
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static int psp_v3_1_init_microcode(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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char ucode_prefix[30];
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int err = 0;
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DRM_DEBUG("\n");
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amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
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err = psp_init_sos_microcode(psp, ucode_prefix);
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if (err)
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return err;
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err = psp_init_asd_microcode(psp, ucode_prefix);
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if (err)
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return err;
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return 0;
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}
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static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
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{
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int ret;
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uint32_t psp_gfxdrv_command_reg = 0;
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struct amdgpu_device *adev = psp->adev;
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uint32_t sol_reg;
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/* Check sOS sign of life register to confirm sys driver and sOS
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* are already been loaded.
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*/
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sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
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if (sol_reg)
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return 0;
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/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
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0x80000000, 0x80000000, false);
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if (ret)
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return ret;
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/* Copy PSP System Driver binary to memory */
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psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
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/* Provide the sys driver to bootloader */
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
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(uint32_t)(psp->fw_pri_mc_addr >> 20));
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psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
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psp_gfxdrv_command_reg);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
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0x80000000, 0x80000000, false);
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return ret;
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}
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static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
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{
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int ret;
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unsigned int psp_gfxdrv_command_reg = 0;
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struct amdgpu_device *adev = psp->adev;
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uint32_t sol_reg;
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/* Check sOS sign of life register to confirm sys driver and sOS
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* are already been loaded.
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*/
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sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
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if (sol_reg)
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return 0;
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/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
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0x80000000, 0x80000000, false);
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if (ret)
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return ret;
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/* Copy Secure OS binary to PSP memory */
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psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
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/* Provide the PSP secure OS to bootloader */
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
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(uint32_t)(psp->fw_pri_mc_addr >> 20));
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psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
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psp_gfxdrv_command_reg);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
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RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
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0, true);
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return ret;
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}
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static void psp_v3_1_reroute_ih(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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uint32_t tmp;
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/* Change IH ring for VMC */
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tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
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tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
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tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
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mdelay(20);
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psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
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0x80000000, 0x8000FFFF, false);
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/* Change IH ring for UMC */
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tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
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tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
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mdelay(20);
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psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
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0x80000000, 0x8000FFFF, false);
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}
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static int psp_v3_1_ring_create(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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unsigned int psp_ring_reg = 0;
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struct psp_ring *ring = &psp->km_ring;
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struct amdgpu_device *adev = psp->adev;
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psp_v3_1_reroute_ih(psp);
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if (amdgpu_sriov_vf(adev)) {
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ring->ring_wptr = 0;
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ret = psp_v3_1_ring_stop(psp, ring_type);
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if (ret) {
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DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");
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return ret;
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}
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/* Write low address of the ring to C2PMSG_102 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_103 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
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/* No size initialization for sriov */
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/* Write the ring initialization command to C2PMSG_101 */
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psp_ring_reg = ring_type;
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psp_ring_reg = psp_ring_reg << 16;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
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/* there might be hardware handshake issue which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_101 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
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mmMP0_SMN_C2PMSG_101), 0x80000000,
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0x8000FFFF, false);
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} else {
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/* Write low address of the ring to C2PMSG_69 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_70 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
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/* Write size of ring to C2PMSG_71 */
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psp_ring_reg = ring->ring_size;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
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/* Write the ring initialization command to C2PMSG_64 */
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psp_ring_reg = ring_type;
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psp_ring_reg = psp_ring_reg << 16;
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
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/* there might be hardware handshake issue which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_64 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
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mmMP0_SMN_C2PMSG_64), 0x80000000,
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0x8000FFFF, false);
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}
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return ret;
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}
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static int psp_v3_1_ring_stop(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct amdgpu_device *adev = psp->adev;
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/* Write the ring destroy command*/
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if (amdgpu_sriov_vf(adev))
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
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GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
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else
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
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GFX_CTRL_CMD_ID_DESTROY_RINGS);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) */
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if (amdgpu_sriov_vf(adev))
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
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0x80000000, 0x80000000, false);
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else
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
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0x80000000, 0x80000000, false);
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return ret;
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}
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static int psp_v3_1_ring_destroy(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring = &psp->km_ring;
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struct amdgpu_device *adev = psp->adev;
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ret = psp_v3_1_ring_stop(psp, ring_type);
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if (ret)
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DRM_ERROR("Fail to stop psp ring\n");
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amdgpu_bo_free_kernel(&adev->firmware.rbuf,
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&ring->ring_mem_mc_addr,
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(void **)&ring->ring_mem);
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return ret;
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}
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static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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uint32_t reg;
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reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);
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return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
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}
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static int psp_v3_1_mode1_reset(struct psp_context *psp)
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{
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int ret;
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uint32_t offset;
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struct amdgpu_device *adev = psp->adev;
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offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
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ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
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if (ret) {
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DRM_INFO("psp is not working correctly before mode1 reset!\n");
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return -EINVAL;
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}
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/*send the mode 1 reset command*/
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WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
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msleep(500);
|
||
|
|
|
||
|
|
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
|
||
|
|
|
||
|
|
ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
DRM_INFO("psp mode 1 reset failed!\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
DRM_INFO("psp mode1 reset succeed \n");
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
|
||
|
|
{
|
||
|
|
uint32_t data;
|
||
|
|
struct amdgpu_device *adev = psp->adev;
|
||
|
|
|
||
|
|
if (amdgpu_sriov_vf(adev))
|
||
|
|
data = psp->km_ring.ring_wptr;
|
||
|
|
else
|
||
|
|
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
|
||
|
|
return data;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)
|
||
|
|
{
|
||
|
|
struct amdgpu_device *adev = psp->adev;
|
||
|
|
|
||
|
|
if (amdgpu_sriov_vf(adev)) {
|
||
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
|
||
|
|
/* send interrupt to PSP for SRIOV ring write pointer update */
|
||
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
|
||
|
|
GFX_CTRL_CMD_ID_CONSUME_CMD);
|
||
|
|
psp->km_ring.ring_wptr = value;
|
||
|
|
} else
|
||
|
|
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct psp_funcs psp_v3_1_funcs = {
|
||
|
|
.init_microcode = psp_v3_1_init_microcode,
|
||
|
|
.bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
|
||
|
|
.bootloader_load_sos = psp_v3_1_bootloader_load_sos,
|
||
|
|
.ring_create = psp_v3_1_ring_create,
|
||
|
|
.ring_stop = psp_v3_1_ring_stop,
|
||
|
|
.ring_destroy = psp_v3_1_ring_destroy,
|
||
|
|
.smu_reload_quirk = psp_v3_1_smu_reload_quirk,
|
||
|
|
.mode1_reset = psp_v3_1_mode1_reset,
|
||
|
|
.ring_get_wptr = psp_v3_1_ring_get_wptr,
|
||
|
|
.ring_set_wptr = psp_v3_1_ring_set_wptr,
|
||
|
|
};
|
||
|
|
|
||
|
|
void psp_v3_1_set_psp_funcs(struct psp_context *psp)
|
||
|
|
{
|
||
|
|
psp->funcs = &psp_v3_1_funcs;
|
||
|
|
}
|