304 lines
8.1 KiB
C
304 lines
8.1 KiB
C
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "smu_v13_0_10.h"
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#include "amdgpu_reset.h"
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#include "amdgpu_dpm.h"
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#include "amdgpu_job.h"
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#include "amdgpu_ring.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_psp.h"
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static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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if (adev->pm.fw_version >= 0x00502005 && !amdgpu_sriov_vf(adev))
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return true;
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return false;
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}
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static struct amdgpu_reset_handler *
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smu_v13_0_10_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *reset_context)
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{
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struct amdgpu_reset_handler *handler;
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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if (reset_context->method != AMD_RESET_METHOD_NONE) {
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list_for_each_entry(handler, &reset_ctl->reset_handlers,
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handler_list) {
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if (handler->reset_method == reset_context->method)
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return handler;
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}
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}
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if (smu_v13_0_10_is_mode2_default(reset_ctl) &&
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amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_MODE2) {
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list_for_each_entry (handler, &reset_ctl->reset_handlers,
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handler_list) {
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if (handler->reset_method == AMD_RESET_METHOD_MODE2)
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return handler;
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}
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}
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return NULL;
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}
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static int smu_v13_0_10_mode2_suspend_ip(struct amdgpu_device *adev)
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{
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int r, i;
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amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
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amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
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for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
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if (!(adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_GFX ||
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adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_SDMA ||
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adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_MES))
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continue;
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r = adev->ip_blocks[i].version->funcs->suspend(adev);
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if (r) {
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dev_err(adev->dev,
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"suspend of IP block <%s> failed %d\n",
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adev->ip_blocks[i].version->funcs->name, r);
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return r;
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}
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adev->ip_blocks[i].status.hw = false;
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}
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return r;
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}
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static int
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smu_v13_0_10_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *reset_context)
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{
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int r = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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if (!amdgpu_sriov_vf(adev))
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r = smu_v13_0_10_mode2_suspend_ip(adev);
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return r;
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}
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static int smu_v13_0_10_mode2_reset(struct amdgpu_device *adev)
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{
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return amdgpu_dpm_mode2_reset(adev);
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}
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static void smu_v13_0_10_async_reset(struct work_struct *work)
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{
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struct amdgpu_reset_handler *handler;
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struct amdgpu_reset_control *reset_ctl =
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container_of(work, struct amdgpu_reset_control, reset_work);
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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list_for_each_entry(handler, &reset_ctl->reset_handlers,
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handler_list) {
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if (handler->reset_method == reset_ctl->active_reset) {
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dev_dbg(adev->dev, "Resetting device\n");
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handler->do_reset(adev);
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break;
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}
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}
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}
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static int
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smu_v13_0_10_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *reset_context)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
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int r;
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r = smu_v13_0_10_mode2_reset(adev);
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if (r) {
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dev_err(adev->dev,
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"ASIC reset failed with error, %d ", r);
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}
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return r;
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}
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static int smu_v13_0_10_mode2_restore_ip(struct amdgpu_device *adev)
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{
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int i, r;
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struct psp_context *psp = &adev->psp;
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struct amdgpu_firmware_info *ucode;
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struct amdgpu_firmware_info *ucode_list[2];
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int ucode_count = 0;
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for (i = 0; i < adev->firmware.max_ucodes; i++) {
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ucode = &adev->firmware.ucode[i];
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switch (ucode->ucode_id) {
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case AMDGPU_UCODE_ID_IMU_I:
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case AMDGPU_UCODE_ID_IMU_D:
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ucode_list[ucode_count++] = ucode;
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break;
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default:
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break;
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}
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}
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r = psp_load_fw_list(psp, ucode_list, ucode_count);
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if (r) {
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dev_err(adev->dev, "IMU ucode load failed after mode2 reset\n");
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return r;
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}
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r = psp_rlc_autoload_start(psp);
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if (r) {
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DRM_ERROR("Failed to start rlc autoload after mode2 reset\n");
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return r;
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}
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amdgpu_dpm_enable_gfx_features(adev);
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for (i = 0; i < adev->num_ip_blocks; i++) {
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if (!(adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_GFX ||
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adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_MES ||
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adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_SDMA))
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continue;
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r = adev->ip_blocks[i].version->funcs->resume(adev);
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if (r) {
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dev_err(adev->dev,
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"resume of IP block <%s> failed %d\n",
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adev->ip_blocks[i].version->funcs->name, r);
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return r;
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}
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adev->ip_blocks[i].status.hw = true;
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}
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for (i = 0; i < adev->num_ip_blocks; i++) {
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if (!(adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_GFX ||
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adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_MES ||
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adev->ip_blocks[i].version->type ==
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AMD_IP_BLOCK_TYPE_SDMA))
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continue;
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if (adev->ip_blocks[i].version->funcs->late_init) {
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r = adev->ip_blocks[i].version->funcs->late_init(
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(void *)adev);
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if (r) {
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dev_err(adev->dev,
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"late_init of IP block <%s> failed %d after reset\n",
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adev->ip_blocks[i].version->funcs->name,
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r);
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return r;
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}
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}
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adev->ip_blocks[i].status.late_initialized = true;
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}
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amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
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amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
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return r;
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}
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static int
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smu_v13_0_10_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
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struct amdgpu_reset_context *reset_context)
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{
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int r;
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struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl->handle;
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dev_info(tmp_adev->dev,
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"GPU reset succeeded, trying to resume\n");
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r = smu_v13_0_10_mode2_restore_ip(tmp_adev);
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if (r)
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goto end;
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amdgpu_register_gpu_instance(tmp_adev);
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/* Resume RAS */
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amdgpu_ras_resume(tmp_adev);
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amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
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r = amdgpu_ib_ring_tests(tmp_adev);
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if (r) {
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dev_err(tmp_adev->dev,
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"ib ring test failed (%d).\n", r);
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r = -EAGAIN;
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goto end;
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}
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end:
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if (r)
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return -EAGAIN;
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else
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return r;
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}
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static struct amdgpu_reset_handler smu_v13_0_10_mode2_handler = {
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.reset_method = AMD_RESET_METHOD_MODE2,
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.prepare_env = NULL,
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.prepare_hwcontext = smu_v13_0_10_mode2_prepare_hwcontext,
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.perform_reset = smu_v13_0_10_mode2_perform_reset,
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.restore_hwcontext = smu_v13_0_10_mode2_restore_hwcontext,
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.restore_env = NULL,
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.do_reset = smu_v13_0_10_mode2_reset,
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};
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int smu_v13_0_10_reset_init(struct amdgpu_device *adev)
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{
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struct amdgpu_reset_control *reset_ctl;
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reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
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if (!reset_ctl)
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return -ENOMEM;
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reset_ctl->handle = adev;
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reset_ctl->async_reset = smu_v13_0_10_async_reset;
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reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
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reset_ctl->get_reset_handler = smu_v13_0_10_get_reset_handler;
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INIT_LIST_HEAD(&reset_ctl->reset_handlers);
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INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
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/* Only mode2 is handled through reset control now */
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amdgpu_reset_add_handler(reset_ctl, &smu_v13_0_10_mode2_handler);
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adev->reset_cntl = reset_ctl;
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return 0;
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}
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int smu_v13_0_10_reset_fini(struct amdgpu_device *adev)
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{
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kfree(adev->reset_cntl);
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adev->reset_cntl = NULL;
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return 0;
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}
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