2023-08-30 17:31:07 +02:00
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __UMC_V8_10_H__
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#define __UMC_V8_10_H__
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#include "soc15_common.h"
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#include "amdgpu.h"
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/* number of umc channel instance with memory map register access */
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#define UMC_V8_10_CHANNEL_INSTANCE_NUM 2
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/* number of umc instance with memory map register access */
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#define UMC_V8_10_UMC_INSTANCE_NUM 2
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/* Total channel instances for all available umc nodes */
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#define UMC_V8_10_TOTAL_CHANNEL_NUM(adev) \
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2023-10-24 12:59:35 +02:00
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(UMC_V8_10_CHANNEL_INSTANCE_NUM * UMC_V8_10_UMC_INSTANCE_NUM * \
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(adev)->gmc.num_umc - hweight32((adev)->gmc.m_half_use) * 2)
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2023-08-30 17:31:07 +02:00
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/* UMC regiser per channel offset */
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#define UMC_V8_10_PER_CHANNEL_OFFSET 0x400
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/* EccErrCnt max value */
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#define UMC_V8_10_CE_CNT_MAX 0xffff
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/* umc ce interrupt threshold */
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#define UUMC_V8_10_CE_INT_THRESHOLD 0xffff
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/* umc ce count initial value */
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#define UMC_V8_10_CE_CNT_INIT (UMC_V8_10_CE_CNT_MAX - UUMC_V8_10_CE_INT_THRESHOLD)
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#define UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM 4
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/* The C5 bit in NA address */
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#define UMC_V8_10_NA_C5_BIT 14
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/* Map to swizzle mode address */
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#define SWIZZLE_MODE_TMP_ADDR(na, ch_num, ch_idx) \
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((((na) >> 10) * (ch_num) + (ch_idx)) << 10)
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#define SWIZZLE_MODE_ADDR_HI(addr, col_bit) \
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(((addr) >> ((col_bit) + 2)) << ((col_bit) + 2))
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#define SWIZZLE_MODE_ADDR_MID(na, col_bit) ((((na) >> 8) & 0x3) << (col_bit))
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#define SWIZZLE_MODE_ADDR_LOW(addr, col_bit) \
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((((addr) >> 10) & ((0x1ULL << (col_bit - 8)) - 1)) << 8)
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#define SWIZZLE_MODE_ADDR_LSB(na) ((na) & 0xFF)
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extern struct amdgpu_umc_ras umc_v8_10_ras;
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extern const uint32_t
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umc_v8_10_channel_idx_tbl[]
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[UMC_V8_10_UMC_INSTANCE_NUM]
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[UMC_V8_10_CHANNEL_INSTANCE_NUM];
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extern const uint32_t
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umc_v8_10_channel_idx_tbl_ext0[]
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[UMC_V8_10_UMC_INSTANCE_NUM]
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[UMC_V8_10_CHANNEL_INSTANCE_NUM];
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#endif
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