506 lines
13 KiB
C
506 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/**************************************************************************
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* Copyright (c) 2011, Intel Corporation.
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* All Rights Reserved.
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*
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**************************************************************************/
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#include <linux/delay.h>
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#include <linux/dmi.h>
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#include <linux/module.h>
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#include <drm/drm.h>
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#include "intel_bios.h"
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#include "mid_bios.h"
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#include "psb_drv.h"
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#include "psb_intel_reg.h"
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#include "psb_reg.h"
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static int oaktrail_output_init(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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if (dev_priv->iLVDS_enable)
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oaktrail_lvds_init(dev, &dev_priv->mode_dev);
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else
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dev_err(dev->dev, "DSI is not supported\n");
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if (dev_priv->hdmi_priv)
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oaktrail_hdmi_init(dev, &dev_priv->mode_dev);
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psb_intel_sdvo_init(dev, SDVOB);
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return 0;
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}
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/*
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* Provide the low level interfaces for the Moorestown backlight
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*/
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#define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
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#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
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#define BLC_PWM_FREQ_CALC_CONSTANT 32
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#define MHz 1000000
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#define BLC_ADJUSTMENT_MAX 100
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static void oaktrail_set_brightness(struct drm_device *dev, int level)
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{
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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u32 blc_pwm_ctl;
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u32 max_pwm_blc;
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if (gma_power_begin(dev, 0)) {
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/* Calculate and set the brightness value */
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max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
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blc_pwm_ctl = level * max_pwm_blc / 100;
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/* Adjust the backlight level with the percent in
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* dev_priv->blc_adj1;
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*/
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blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
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blc_pwm_ctl = blc_pwm_ctl / 100;
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/* Adjust the backlight level with the percent in
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* dev_priv->blc_adj2;
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*/
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blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
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blc_pwm_ctl = blc_pwm_ctl / 100;
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/* force PWM bit on */
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REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
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REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);
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gma_power_end(dev);
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}
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}
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static int oaktrail_backlight_init(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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unsigned long core_clock;
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u16 bl_max_freq;
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uint32_t value;
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uint32_t blc_pwm_precision_factor;
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dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
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dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
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bl_max_freq = 256;
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/* this needs to be set elsewhere */
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blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;
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core_clock = dev_priv->core_freq;
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value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
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value *= blc_pwm_precision_factor;
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value /= bl_max_freq;
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value /= blc_pwm_precision_factor;
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if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
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return -ERANGE;
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if (gma_power_begin(dev, false)) {
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REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
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REG_WRITE(BLC_PWM_CTL, value | (value << 16));
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gma_power_end(dev);
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}
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oaktrail_set_brightness(dev, PSB_MAX_BRIGHTNESS);
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return 0;
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}
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/*
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* Provide the Moorestown specific chip logic and low level methods
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* for power management
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*/
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/**
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* oaktrail_save_display_registers - save registers lost on suspend
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* @dev: our DRM device
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*
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* Save the state we need in order to be able to restore the interface
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* upon resume from suspend
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*/
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static int oaktrail_save_display_registers(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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struct psb_save_area *regs = &dev_priv->regs;
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struct psb_pipe *p = ®s->pipe[0];
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int i;
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u32 pp_stat;
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/* Display arbitration control + watermarks */
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regs->psb.saveDSPARB = PSB_RVDC32(DSPARB);
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regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1);
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regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2);
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regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3);
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regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4);
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regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5);
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regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6);
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regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
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/* Pipe & plane A info */
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p->conf = PSB_RVDC32(PIPEACONF);
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p->src = PSB_RVDC32(PIPEASRC);
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p->fp0 = PSB_RVDC32(MRST_FPA0);
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p->fp1 = PSB_RVDC32(MRST_FPA1);
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p->dpll = PSB_RVDC32(MRST_DPLL_A);
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p->htotal = PSB_RVDC32(HTOTAL_A);
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p->hblank = PSB_RVDC32(HBLANK_A);
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p->hsync = PSB_RVDC32(HSYNC_A);
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p->vtotal = PSB_RVDC32(VTOTAL_A);
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p->vblank = PSB_RVDC32(VBLANK_A);
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p->vsync = PSB_RVDC32(VSYNC_A);
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regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
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p->cntr = PSB_RVDC32(DSPACNTR);
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p->stride = PSB_RVDC32(DSPASTRIDE);
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p->addr = PSB_RVDC32(DSPABASE);
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p->surf = PSB_RVDC32(DSPASURF);
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p->linoff = PSB_RVDC32(DSPALINOFF);
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p->tileoff = PSB_RVDC32(DSPATILEOFF);
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/* Save cursor regs */
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regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
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regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
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regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
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/* Save palette (gamma) */
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for (i = 0; i < 256; i++)
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p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2));
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if (dev_priv->hdmi_priv)
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oaktrail_hdmi_save(dev);
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/* Save performance state */
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regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
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/* LVDS state */
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regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
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regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
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regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
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regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
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regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
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regs->psb.saveLVDS = PSB_RVDC32(LVDS);
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regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
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regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
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regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
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regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
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/* HW overlay */
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regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD);
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regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
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regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
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regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
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regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
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regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
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regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
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/* DPST registers */
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regs->psb.saveHISTOGRAM_INT_CONTROL_REG =
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PSB_RVDC32(HISTOGRAM_INT_CONTROL);
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regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG =
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PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
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regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);
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if (dev_priv->iLVDS_enable) {
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/* Shut down the panel */
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PSB_WVDC32(0, PP_CONTROL);
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do {
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pp_stat = PSB_RVDC32(PP_STATUS);
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} while (pp_stat & 0x80000000);
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/* Turn off the plane */
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PSB_WVDC32(0x58000000, DSPACNTR);
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/* Trigger the plane disable */
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PSB_WVDC32(0, DSPASURF);
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/* Wait ~4 ticks */
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msleep(4);
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/* Turn off pipe */
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PSB_WVDC32(0x0, PIPEACONF);
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/* Wait ~8 ticks */
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msleep(8);
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/* Turn off PLLs */
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PSB_WVDC32(0, MRST_DPLL_A);
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}
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return 0;
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}
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/**
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* oaktrail_restore_display_registers - restore lost register state
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* @dev: our DRM device
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*
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* Restore register state that was lost during suspend and resume.
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*/
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static int oaktrail_restore_display_registers(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
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struct psb_save_area *regs = &dev_priv->regs;
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struct psb_pipe *p = ®s->pipe[0];
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u32 pp_stat;
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int i;
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/* Display arbitration + watermarks */
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PSB_WVDC32(regs->psb.saveDSPARB, DSPARB);
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PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
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PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2);
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PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3);
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PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4);
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PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5);
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PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6);
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PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT);
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/* Make sure VGA plane is off. it initializes to on after reset!*/
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PSB_WVDC32(0x80000000, VGACNTRL);
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/* set the plls */
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PSB_WVDC32(p->fp0, MRST_FPA0);
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PSB_WVDC32(p->fp1, MRST_FPA1);
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/* Actually enable it */
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PSB_WVDC32(p->dpll, MRST_DPLL_A);
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udelay(150);
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/* Restore mode */
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PSB_WVDC32(p->htotal, HTOTAL_A);
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PSB_WVDC32(p->hblank, HBLANK_A);
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PSB_WVDC32(p->hsync, HSYNC_A);
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PSB_WVDC32(p->vtotal, VTOTAL_A);
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PSB_WVDC32(p->vblank, VBLANK_A);
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PSB_WVDC32(p->vsync, VSYNC_A);
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PSB_WVDC32(p->src, PIPEASRC);
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PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);
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/* Restore performance mode*/
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PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE);
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/* Enable the pipe*/
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if (dev_priv->iLVDS_enable)
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PSB_WVDC32(p->conf, PIPEACONF);
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/* Set up the plane*/
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PSB_WVDC32(p->linoff, DSPALINOFF);
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PSB_WVDC32(p->stride, DSPASTRIDE);
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PSB_WVDC32(p->tileoff, DSPATILEOFF);
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/* Enable the plane */
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PSB_WVDC32(p->cntr, DSPACNTR);
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PSB_WVDC32(p->surf, DSPASURF);
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/* Enable Cursor A */
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PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
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PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS);
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PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE);
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/* Restore palette (gamma) */
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for (i = 0; i < 256; i++)
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PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2));
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if (dev_priv->hdmi_priv)
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oaktrail_hdmi_restore(dev);
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if (dev_priv->iLVDS_enable) {
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PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
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PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/
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PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL);
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PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
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PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
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PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL);
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PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON);
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PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF);
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PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE);
|
||
|
|
PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Wait for cycle delay */
|
||
|
|
do {
|
||
|
|
pp_stat = PSB_RVDC32(PP_STATUS);
|
||
|
|
} while (pp_stat & 0x08000000);
|
||
|
|
|
||
|
|
/* Wait for panel power up */
|
||
|
|
do {
|
||
|
|
pp_stat = PSB_RVDC32(PP_STATUS);
|
||
|
|
} while (pp_stat & 0x10000000);
|
||
|
|
|
||
|
|
/* Restore HW overlay */
|
||
|
|
PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD);
|
||
|
|
PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0);
|
||
|
|
PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1);
|
||
|
|
PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2);
|
||
|
|
PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3);
|
||
|
|
PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4);
|
||
|
|
PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5);
|
||
|
|
|
||
|
|
/* DPST registers */
|
||
|
|
PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG,
|
||
|
|
HISTOGRAM_INT_CONTROL);
|
||
|
|
PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG,
|
||
|
|
HISTOGRAM_LOGIC_CONTROL);
|
||
|
|
PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* oaktrail_power_down - power down the display island
|
||
|
|
* @dev: our DRM device
|
||
|
|
*
|
||
|
|
* Power down the display interface of our device
|
||
|
|
*/
|
||
|
|
static int oaktrail_power_down(struct drm_device *dev)
|
||
|
|
{
|
||
|
|
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
||
|
|
u32 pwr_mask ;
|
||
|
|
u32 pwr_sts;
|
||
|
|
|
||
|
|
pwr_mask = PSB_PWRGT_DISPLAY_MASK;
|
||
|
|
outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);
|
||
|
|
|
||
|
|
while (true) {
|
||
|
|
pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
|
||
|
|
if ((pwr_sts & pwr_mask) == pwr_mask)
|
||
|
|
break;
|
||
|
|
else
|
||
|
|
udelay(10);
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* oaktrail_power_up
|
||
|
|
*
|
||
|
|
* Restore power to the specified island(s) (powergating)
|
||
|
|
*/
|
||
|
|
static int oaktrail_power_up(struct drm_device *dev)
|
||
|
|
{
|
||
|
|
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
||
|
|
u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
|
||
|
|
u32 pwr_sts, pwr_cnt;
|
||
|
|
|
||
|
|
pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
|
||
|
|
pwr_cnt &= ~pwr_mask;
|
||
|
|
outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));
|
||
|
|
|
||
|
|
while (true) {
|
||
|
|
pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
|
||
|
|
if ((pwr_sts & pwr_mask) == 0)
|
||
|
|
break;
|
||
|
|
else
|
||
|
|
udelay(10);
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Oaktrail */
|
||
|
|
static const struct psb_offset oaktrail_regmap[2] = {
|
||
|
|
{
|
||
|
|
.fp0 = MRST_FPA0,
|
||
|
|
.fp1 = MRST_FPA1,
|
||
|
|
.cntr = DSPACNTR,
|
||
|
|
.conf = PIPEACONF,
|
||
|
|
.src = PIPEASRC,
|
||
|
|
.dpll = MRST_DPLL_A,
|
||
|
|
.htotal = HTOTAL_A,
|
||
|
|
.hblank = HBLANK_A,
|
||
|
|
.hsync = HSYNC_A,
|
||
|
|
.vtotal = VTOTAL_A,
|
||
|
|
.vblank = VBLANK_A,
|
||
|
|
.vsync = VSYNC_A,
|
||
|
|
.stride = DSPASTRIDE,
|
||
|
|
.size = DSPASIZE,
|
||
|
|
.pos = DSPAPOS,
|
||
|
|
.surf = DSPASURF,
|
||
|
|
.addr = MRST_DSPABASE,
|
||
|
|
.base = MRST_DSPABASE,
|
||
|
|
.status = PIPEASTAT,
|
||
|
|
.linoff = DSPALINOFF,
|
||
|
|
.tileoff = DSPATILEOFF,
|
||
|
|
.palette = PALETTE_A,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.fp0 = FPB0,
|
||
|
|
.fp1 = FPB1,
|
||
|
|
.cntr = DSPBCNTR,
|
||
|
|
.conf = PIPEBCONF,
|
||
|
|
.src = PIPEBSRC,
|
||
|
|
.dpll = DPLL_B,
|
||
|
|
.htotal = HTOTAL_B,
|
||
|
|
.hblank = HBLANK_B,
|
||
|
|
.hsync = HSYNC_B,
|
||
|
|
.vtotal = VTOTAL_B,
|
||
|
|
.vblank = VBLANK_B,
|
||
|
|
.vsync = VSYNC_B,
|
||
|
|
.stride = DSPBSTRIDE,
|
||
|
|
.size = DSPBSIZE,
|
||
|
|
.pos = DSPBPOS,
|
||
|
|
.surf = DSPBSURF,
|
||
|
|
.addr = DSPBBASE,
|
||
|
|
.base = DSPBBASE,
|
||
|
|
.status = PIPEBSTAT,
|
||
|
|
.linoff = DSPBLINOFF,
|
||
|
|
.tileoff = DSPBTILEOFF,
|
||
|
|
.palette = PALETTE_B,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static int oaktrail_chip_setup(struct drm_device *dev)
|
||
|
|
{
|
||
|
|
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
dev_priv->use_msi = true;
|
||
|
|
dev_priv->regmap = oaktrail_regmap;
|
||
|
|
|
||
|
|
ret = mid_chip_setup(dev);
|
||
|
|
if (ret < 0)
|
||
|
|
return ret;
|
||
|
|
if (!dev_priv->has_gct) {
|
||
|
|
/* Now pull the BIOS data */
|
||
|
|
psb_intel_opregion_init(dev);
|
||
|
|
psb_intel_init_bios(dev);
|
||
|
|
}
|
||
|
|
gma_intel_setup_gmbus(dev);
|
||
|
|
oaktrail_hdmi_setup(dev);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void oaktrail_teardown(struct drm_device *dev)
|
||
|
|
{
|
||
|
|
struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
|
||
|
|
|
||
|
|
gma_intel_teardown_gmbus(dev);
|
||
|
|
oaktrail_hdmi_teardown(dev);
|
||
|
|
if (!dev_priv->has_gct)
|
||
|
|
psb_intel_destroy_bios(dev);
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct psb_ops oaktrail_chip_ops = {
|
||
|
|
.name = "Oaktrail",
|
||
|
|
.pipes = 2,
|
||
|
|
.crtcs = 2,
|
||
|
|
.hdmi_mask = (1 << 1),
|
||
|
|
.lvds_mask = (1 << 0),
|
||
|
|
.sdvo_mask = (1 << 1),
|
||
|
|
.cursor_needs_phys = 0,
|
||
|
|
.sgx_offset = MRST_SGX_OFFSET,
|
||
|
|
|
||
|
|
.chip_setup = oaktrail_chip_setup,
|
||
|
|
.chip_teardown = oaktrail_teardown,
|
||
|
|
.crtc_helper = &oaktrail_helper_funcs,
|
||
|
|
|
||
|
|
.output_init = oaktrail_output_init,
|
||
|
|
|
||
|
|
.backlight_init = oaktrail_backlight_init,
|
||
|
|
.backlight_set = oaktrail_set_brightness,
|
||
|
|
.backlight_name = "oaktrail-bl",
|
||
|
|
|
||
|
|
.save_regs = oaktrail_save_display_registers,
|
||
|
|
.restore_regs = oaktrail_restore_display_registers,
|
||
|
|
.save_crtc = gma_crtc_save,
|
||
|
|
.restore_crtc = gma_crtc_restore,
|
||
|
|
.power_down = oaktrail_power_down,
|
||
|
|
.power_up = oaktrail_power_up,
|
||
|
|
|
||
|
|
.i2c_bus = 1,
|
||
|
|
};
|