87 lines
4.1 KiB
C
87 lines
4.1 KiB
C
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __INTEL_DP_AUX_REGS_H__
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#define __INTEL_DP_AUX_REGS_H__
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#include "intel_display_reg_defs.h"
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/*
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* The aux channel provides a way to talk to the signal sink for DDC etc. Max
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* packet size supported is 20 bytes in each direction, hence the 5 fixed data
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* registers
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*/
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#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
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#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
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#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
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#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
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#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
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#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
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#define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
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#define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
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#define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
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#define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
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#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
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_DPA_AUX_CH_CTL, \
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_DPB_AUX_CH_CTL, \
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0, /* port/aux_ch C is non-existent */ \
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_XELPDP_USBC1_AUX_CH_CTL, \
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_XELPDP_USBC2_AUX_CH_CTL, \
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_XELPDP_USBC3_AUX_CH_CTL, \
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_XELPDP_USBC4_AUX_CH_CTL))
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#define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214
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#define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414
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#define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614
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#define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814
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#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
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_DPA_AUX_CH_DATA1, \
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_DPB_AUX_CH_DATA1, \
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0, /* port/aux_ch C is non-existent */ \
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_XELPDP_USBC1_AUX_CH_DATA1, \
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_XELPDP_USBC2_AUX_CH_DATA1, \
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_XELPDP_USBC3_AUX_CH_DATA1, \
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_XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
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#define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31)
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#define DP_AUX_CH_CTL_DONE REG_BIT(30)
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#define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29)
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#define DP_AUX_CH_CTL_TIME_OUT_ERROR REG_BIT(28)
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#define DP_AUX_CH_CTL_TIME_OUT_MASK REG_GENMASK(27, 26)
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#define DP_AUX_CH_CTL_TIME_OUT_400us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 0)
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#define DP_AUX_CH_CTL_TIME_OUT_600us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 1)
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#define DP_AUX_CH_CTL_TIME_OUT_800us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 2)
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#define DP_AUX_CH_CTL_TIME_OUT_MAX REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 3) /* Varies per platform */
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#define DP_AUX_CH_CTL_RECEIVE_ERROR REG_BIT(25)
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#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK REG_GENMASK(24, 20)
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#define DP_AUX_CH_CTL_MESSAGE_SIZE(x) REG_FIELD_PREP(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, (x))
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#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK REG_GENMASK(19, 16) /* pre-skl */
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#define DP_AUX_CH_CTL_PRECHARGE_2US(x) REG_FIELD_PREP(DP_AUX_CH_CTL_PRECHARGE_2US_MASK, (x))
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#define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19) /* mtl+ */
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#define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18) /* mtl+ */
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#define DP_AUX_CH_CTL_AUX_AKSV_SELECT REG_BIT(15)
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#define DP_AUX_CH_CTL_MANCHESTER_TEST REG_BIT(14) /* pre-hsw */
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#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL REG_BIT(14) /* skl+ */
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#define DP_AUX_CH_CTL_SYNC_TEST REG_BIT(13) /* pre-hsw */
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#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL REG_BIT(13) /* skl+ */
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#define DP_AUX_CH_CTL_DEGLITCH_TEST REG_BIT(12) /* pre-hsw */
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#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL REG_BIT(12) /* skl+ */
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#define DP_AUX_CH_CTL_PRECHARGE_TEST REG_BIT(11) /* pre-hsw */
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#define DP_AUX_CH_CTL_TBT_IO REG_BIT(11) /* icl+ */
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#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK REG_GENMASK(10, 0) /* pre-skl */
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#define DP_AUX_CH_CTL_BIT_CLOCK_2X(x) REG_FIELD_PREP(DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK, (x))
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#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK REG_GENMASK(9, 5) /* skl+ */
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#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK, (c) - 1)
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#define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /* skl+ */
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#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
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#endif /* __INTEL_DP_AUX_REGS_H__ */
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