66 lines
2.5 KiB
C
66 lines
2.5 KiB
C
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __INTEL_LVDS_REGS_H__
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#define __INTEL_LVDS_REGS_H__
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#include "intel_display_reg_defs.h"
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/* LVDS port control */
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#define LVDS _MMIO(0x61180)
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/*
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* Enables the LVDS port. This bit must be set before DPLLs are enabled, as
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* the DPLL semantics change when the LVDS is assigned to that pipe.
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*/
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#define LVDS_PORT_EN REG_BIT(31)
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/* Selects pipe B for LVDS data. Must be set on pre-965. */
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#define LVDS_PIPE_SEL_MASK REG_BIT(30)
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#define LVDS_PIPE_SEL(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK, (pipe))
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#define LVDS_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29)
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#define LVDS_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(LVDS_PIPE_SEL_MASK_CPT, (pipe))
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/* LVDS dithering flag on 965/g4x platform */
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#define LVDS_ENABLE_DITHER REG_BIT(25)
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/* LVDS sync polarity flags. Set to invert (i.e. negative) */
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#define LVDS_VSYNC_POLARITY REG_BIT(21)
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#define LVDS_HSYNC_POLARITY REG_BIT(20)
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/* Enable border for unscaled (or aspect-scaled) display */
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#define LVDS_BORDER_ENABLE REG_BIT(15)
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/*
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* Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
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* pixel.
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*/
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#define LVDS_A0A2_CLKA_POWER_MASK REG_GENMASK(9, 8)
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#define LVDS_A0A2_CLKA_POWER_DOWN REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 0)
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#define LVDS_A0A2_CLKA_POWER_UP REG_FIELD_PREP(LVDS_A0A2_CLKA_POWER_MASK, 3)
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/*
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* Controls the A3 data pair, which contains the additional LSBs for 24 bit
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* mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
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* on.
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*/
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#define LVDS_A3_POWER_MASK REG_GENMASK(7, 6)
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#define LVDS_A3_POWER_DOWN REG_FIELD_PREP(LVDS_A3_POWER_MASK, 0)
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#define LVDS_A3_POWER_UP REG_FIELD_PREP(LVDS_A3_POWER_MASK, 3)
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/*
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* Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
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* is set.
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*/
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#define LVDS_CLKB_POWER_MASK REG_GENMASK(5, 4)
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#define LVDS_CLKB_POWER_DOWN REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 0)
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#define LVDS_CLKB_POWER_UP REG_FIELD_PREP(LVDS_CLKB_POWER_MASK, 3)
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/*
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* Controls the B0-B3 data pairs. This must be set to match the DPLL p2
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* setting for whether we are in dual-channel mode. The B3 pair will
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* additionally only be powered up when LVDS_A3_POWER_UP is set.
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*/
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#define LVDS_B0B3_POWER_MASK REG_GENMASK(3, 2)
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#define LVDS_B0B3_POWER_DOWN REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 0)
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#define LVDS_B0B3_POWER_UP REG_FIELD_PREP(LVDS_B0B3_POWER_MASK, 3)
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#define PCH_LVDS _MMIO(0xe1180)
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#define LVDS_DETECTED REG_BIT(1)
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#endif /* __INTEL_LVDS_REGS_H__ */
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