2023-08-30 17:31:07 +02:00
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_MG_PHY_REGS__
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#define __INTEL_MG_PHY_REGS__
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#include "intel_display_reg_defs.h"
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#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \
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_MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
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#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C
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#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C
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#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C
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#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C
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#define MG_TX1_LINK_PARAMS(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
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MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
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MG_TX_LINK_PARAMS_TX1LN1_PORT1)
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#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC
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#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC
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#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC
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#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC
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#define MG_TX2_LINK_PARAMS(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
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MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
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MG_TX_LINK_PARAMS_TX2LN1_PORT1)
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#define CRI_USE_FS32 (1 << 5)
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#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C
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#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C
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#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C
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#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C
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#define MG_TX1_PISO_READLOAD(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
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MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
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MG_TX_PISO_READLOAD_TX1LN1_PORT1)
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#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC
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#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC
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#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC
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#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC
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#define MG_TX2_PISO_READLOAD(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
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MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
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MG_TX_PISO_READLOAD_TX2LN1_PORT1)
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#define CRI_CALCINIT (1 << 1)
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#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148
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#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548
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#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148
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#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548
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#define MG_TX1_SWINGCTRL(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
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MG_TX_SWINGCTRL_TX1LN0_PORT2, \
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MG_TX_SWINGCTRL_TX1LN1_PORT1)
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#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8
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#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8
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#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8
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#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8
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#define MG_TX2_SWINGCTRL(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
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MG_TX_SWINGCTRL_TX2LN0_PORT2, \
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MG_TX_SWINGCTRL_TX2LN1_PORT1)
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#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0)
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#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0)
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#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144
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#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544
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#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144
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#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544
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#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144
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#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544
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#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144
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#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544
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#define MG_TX1_DRVCTRL(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \
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MG_TX_DRVCTRL_TX1LN0_TXPORT2, \
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MG_TX_DRVCTRL_TX1LN1_TXPORT1)
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#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4
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#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4
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#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4
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#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4
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#define MG_TX2_DRVCTRL(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \
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MG_TX_DRVCTRL_TX2LN0_PORT2, \
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MG_TX_DRVCTRL_TX2LN1_PORT1)
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#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24)
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#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24)
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#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22)
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#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16)
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#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16)
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#define CRI_LOADGEN_SEL(x) ((x) << 12)
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#define CRI_LOADGEN_SEL_MASK (0x3 << 12)
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#define MG_CLKHUB_LN0_PORT1 0x16839C
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#define MG_CLKHUB_LN1_PORT1 0x16879C
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#define MG_CLKHUB_LN0_PORT2 0x16939C
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#define MG_CLKHUB_LN1_PORT2 0x16979C
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#define MG_CLKHUB(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \
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MG_CLKHUB_LN0_PORT2, \
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MG_CLKHUB_LN1_PORT1)
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#define CFG_LOW_RATE_LKREN_EN (1 << 11)
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#define MG_TX_DCC_TX1LN0_PORT1 0x168110
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#define MG_TX_DCC_TX1LN1_PORT1 0x168510
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#define MG_TX_DCC_TX1LN0_PORT2 0x169110
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#define MG_TX_DCC_TX1LN1_PORT2 0x169510
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#define MG_TX1_DCC(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \
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MG_TX_DCC_TX1LN0_PORT2, \
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MG_TX_DCC_TX1LN1_PORT1)
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#define MG_TX_DCC_TX2LN0_PORT1 0x168090
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#define MG_TX_DCC_TX2LN1_PORT1 0x168490
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#define MG_TX_DCC_TX2LN0_PORT2 0x169090
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#define MG_TX_DCC_TX2LN1_PORT2 0x169490
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#define MG_TX2_DCC(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \
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MG_TX_DCC_TX2LN0_PORT2, \
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MG_TX_DCC_TX2LN1_PORT1)
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#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25)
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#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
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#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
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#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
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#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
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#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
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#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
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#define MG_DP_MODE(ln, tc_port) \
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MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \
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MG_DP_MODE_LN0_ACU_PORT2, \
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MG_DP_MODE_LN1_ACU_PORT1)
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#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
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#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
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#define FIA1_BASE 0x163000
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#define FIA2_BASE 0x16E000
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#define FIA3_BASE 0x16F000
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2023-10-24 12:59:35 +02:00
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#define _FIA(fia) _PICK_EVEN_2RANGES((fia), 1, \
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FIA1_BASE, FIA1_BASE,\
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FIA2_BASE, FIA3_BASE)
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2023-08-30 17:31:07 +02:00
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#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
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/* ICL PHY DFLEX registers */
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#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0)
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#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx)))
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#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx)))
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#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx)))
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#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx)))
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#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx)))
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#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx)))
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#define _MG_REFCLKIN_CTL_PORT1 0x16892C
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#define _MG_REFCLKIN_CTL_PORT2 0x16992C
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#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8)
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#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8)
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#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \
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_MG_REFCLKIN_CTL_PORT1, \
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_MG_REFCLKIN_CTL_PORT2)
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#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8
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#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8
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#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16)
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#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16)
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#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8)
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#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8)
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#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \
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_MG_CLKTOP2_CORECLKCTL1_PORT1, \
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_MG_CLKTOP2_CORECLKCTL1_PORT2)
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#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
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#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
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#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16)
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#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16)
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#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
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#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14)
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#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12)
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#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12)
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#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12)
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#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12)
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#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12)
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#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
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#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8
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#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8)
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#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \
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_MG_CLKTOP2_HSCLKCTL_PORT1, \
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_MG_CLKTOP2_HSCLKCTL_PORT2)
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#define _MG_PLL_DIV0_PORT1 0x168A00
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#define _MG_PLL_DIV0_PORT2 0x169A00
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#define MG_PLL_DIV0_FRACNEN_H (1 << 30)
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#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8)
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#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8
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#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8)
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#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0)
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#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0)
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#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \
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_MG_PLL_DIV0_PORT2)
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#define _MG_PLL_DIV1_PORT1 0x168A04
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#define _MG_PLL_DIV1_PORT2 0x169A04
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#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16)
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#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12)
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#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12)
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#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12)
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#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12)
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#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4)
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#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0)
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#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0)
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#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \
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_MG_PLL_DIV1_PORT2)
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#define _MG_PLL_LF_PORT1 0x168A08
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#define _MG_PLL_LF_PORT2 0x169A08
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#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24)
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#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
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#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
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#define MG_PLL_LF_GAINCTRL(x) ((x) << 16)
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#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
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#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0)
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#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \
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_MG_PLL_LF_PORT2)
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#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C
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#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C
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#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18)
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#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16)
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#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11)
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#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10)
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#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
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#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0)
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#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \
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_MG_PLL_FRAC_LOCK_PORT1, \
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_MG_PLL_FRAC_LOCK_PORT2)
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#define _MG_PLL_SSC_PORT1 0x168A10
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#define _MG_PLL_SSC_PORT2 0x169A10
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#define MG_PLL_SSC_EN (1 << 28)
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#define MG_PLL_SSC_TYPE(x) ((x) << 26)
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#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16)
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#define MG_PLL_SSC_STEPNUM(x) ((x) << 10)
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#define MG_PLL_SSC_FLLEN (1 << 9)
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#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
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#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \
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_MG_PLL_SSC_PORT2)
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#define _MG_PLL_BIAS_PORT1 0x168A14
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#define _MG_PLL_BIAS_PORT2 0x169A14
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#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30)
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#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30)
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#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24)
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#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24)
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#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16)
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#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16)
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#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
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#define MG_PLL_BIAS_CTRIM(x) ((x) << 8)
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#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8)
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#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5)
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#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5)
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#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0)
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#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0)
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#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \
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_MG_PLL_BIAS_PORT2)
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#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18
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#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18
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#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27)
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#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17)
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#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16)
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#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2)
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#define MG_PLL_TDC_TDCSEL(x) ((x) << 0)
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#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \
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_MG_PLL_TDC_COLDST_BIAS_PORT1, \
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_MG_PLL_TDC_COLDST_BIAS_PORT2)
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#endif /* __INTEL_MG_PHY_REGS__ */
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