2023-08-30 17:31:07 +02:00
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#ifndef _INTEL_GUC_SLPC_H_
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#define _INTEL_GUC_SLPC_H_
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#include "intel_guc_submission.h"
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#include "intel_guc_slpc_types.h"
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#define SLPC_MAX_FREQ_MHZ 4250
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struct intel_gt;
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struct drm_printer;
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static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc)
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{
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return guc->slpc.supported;
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}
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static inline bool intel_guc_slpc_is_wanted(struct intel_guc *guc)
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{
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return guc->slpc.selected;
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}
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static inline bool intel_guc_slpc_is_used(struct intel_guc *guc)
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{
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return intel_guc_submission_is_used(guc) && intel_guc_slpc_is_wanted(guc);
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}
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void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc);
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int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
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int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
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void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
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int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val);
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int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);
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int intel_guc_slpc_set_boost_freq(struct intel_guc_slpc *slpc, u32 val);
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int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);
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int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);
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int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p);
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int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val);
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void intel_guc_pm_intrmsk_enable(struct intel_gt *gt);
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void intel_guc_slpc_boost(struct intel_guc_slpc *slpc);
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void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc);
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int intel_guc_slpc_unset_gucrc_mode(struct intel_guc_slpc *slpc);
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int intel_guc_slpc_override_gucrc_mode(struct intel_guc_slpc *slpc, u32 mode);
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2023-10-24 12:59:35 +02:00
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int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val);
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2023-08-30 17:31:07 +02:00
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#endif
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