266 lines
7.9 KiB
C
266 lines
7.9 KiB
C
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/*
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* Copyright 1993-2003 NVIDIA, Corporation
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* Copyright 2007-2009 Stuart Bennett
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "nouveau_drv.h"
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#include "nouveau_reg.h"
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#include "hw.h"
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/****************************************************************************\
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* *
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* The video arbitration routines calculate some "magic" numbers. Fixes *
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* the snow seen when accessing the framebuffer without it. *
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* It just works (I hope). *
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* *
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\****************************************************************************/
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struct nv_fifo_info {
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int lwm;
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int burst;
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};
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struct nv_sim_state {
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int pclk_khz;
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int mclk_khz;
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int nvclk_khz;
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int bpp;
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int mem_page_miss;
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int mem_latency;
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int memory_type;
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int memory_width;
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int two_heads;
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};
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static void
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nv04_calc_arb(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
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{
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int pagemiss, cas, bpp;
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int nvclks, mclks, crtpagemiss;
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int found, mclk_extra, mclk_loop, cbs, m1, p1;
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int mclk_freq, pclk_freq, nvclk_freq;
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int us_m, us_n, us_p, crtc_drain_rate;
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int cpm_us, us_crt, clwm;
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pclk_freq = arb->pclk_khz;
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mclk_freq = arb->mclk_khz;
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nvclk_freq = arb->nvclk_khz;
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pagemiss = arb->mem_page_miss;
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cas = arb->mem_latency;
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bpp = arb->bpp;
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cbs = 128;
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nvclks = 10;
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mclks = 13 + cas;
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mclk_extra = 3;
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found = 0;
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while (!found) {
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found = 1;
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mclk_loop = mclks + mclk_extra;
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us_m = mclk_loop * 1000 * 1000 / mclk_freq;
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us_n = nvclks * 1000 * 1000 / nvclk_freq;
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us_p = nvclks * 1000 * 1000 / pclk_freq;
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crtc_drain_rate = pclk_freq * bpp / 8;
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crtpagemiss = 2;
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crtpagemiss += 1;
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cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
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us_crt = cpm_us + us_m + us_n + us_p;
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clwm = us_crt * crtc_drain_rate / (1000 * 1000);
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clwm++;
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m1 = clwm + cbs - 512;
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p1 = m1 * pclk_freq / mclk_freq;
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p1 = p1 * bpp / 8;
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if ((p1 < m1 && m1 > 0) || clwm > 519) {
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found = !mclk_extra;
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mclk_extra--;
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}
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if (clwm < 384)
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clwm = 384;
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fifo->lwm = clwm;
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fifo->burst = cbs;
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}
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}
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static void
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nv10_calc_arb(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
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{
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int fill_rate, drain_rate;
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int pclks, nvclks, mclks, xclks;
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int pclk_freq, nvclk_freq, mclk_freq;
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int fill_lat, extra_lat;
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int max_burst_o, max_burst_l;
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int fifo_len, min_lwm, max_lwm;
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const int burst_lat = 80; /* Maximum allowable latency due
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* to the CRTC FIFO burst. (ns) */
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pclk_freq = arb->pclk_khz;
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nvclk_freq = arb->nvclk_khz;
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mclk_freq = arb->mclk_khz;
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fill_rate = mclk_freq * arb->memory_width / 8; /* kB/s */
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drain_rate = pclk_freq * arb->bpp / 8; /* kB/s */
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fifo_len = arb->two_heads ? 1536 : 1024; /* B */
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/* Fixed FIFO refill latency. */
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pclks = 4; /* lwm detect. */
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nvclks = 3 /* lwm -> sync. */
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+ 2 /* fbi bus cycles (1 req + 1 busy) */
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+ 1 /* 2 edge sync. may be very close to edge so
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* just put one. */
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+ 1 /* fbi_d_rdv_n */
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+ 1 /* Fbi_d_rdata */
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+ 1; /* crtfifo load */
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mclks = 1 /* 2 edge sync. may be very close to edge so
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* just put one. */
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+ 1 /* arb_hp_req */
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+ 5 /* tiling pipeline */
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+ 2 /* latency fifo */
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+ 2 /* memory request to fbio block */
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+ 7; /* data returned from fbio block */
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/* Need to accumulate 256 bits for read */
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mclks += (arb->memory_type == 0 ? 2 : 1)
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* arb->memory_width / 32;
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fill_lat = mclks * 1000 * 1000 / mclk_freq /* minimum mclk latency */
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+ nvclks * 1000 * 1000 / nvclk_freq /* nvclk latency */
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+ pclks * 1000 * 1000 / pclk_freq; /* pclk latency */
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/* Conditional FIFO refill latency. */
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xclks = 2 * arb->mem_page_miss + mclks /* Extra latency due to
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* the overlay. */
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+ 2 * arb->mem_page_miss /* Extra pagemiss latency. */
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+ (arb->bpp == 32 ? 8 : 4); /* Margin of error. */
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extra_lat = xclks * 1000 * 1000 / mclk_freq;
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if (arb->two_heads)
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/* Account for another CRTC. */
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extra_lat += fill_lat + extra_lat + burst_lat;
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/* FIFO burst */
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/* Max burst not leading to overflows. */
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max_burst_o = (1 + fifo_len - extra_lat * drain_rate / (1000 * 1000))
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* (fill_rate / 1000) / ((fill_rate - drain_rate) / 1000);
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fifo->burst = min(max_burst_o, 1024);
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/* Max burst value with an acceptable latency. */
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max_burst_l = burst_lat * fill_rate / (1000 * 1000);
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fifo->burst = min(max_burst_l, fifo->burst);
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fifo->burst = rounddown_pow_of_two(fifo->burst);
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/* FIFO low watermark */
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min_lwm = (fill_lat + extra_lat) * drain_rate / (1000 * 1000) + 1;
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max_lwm = fifo_len - fifo->burst
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+ fill_lat * drain_rate / (1000 * 1000)
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+ fifo->burst * drain_rate / fill_rate;
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fifo->lwm = min_lwm + 10 * (max_lwm - min_lwm) / 100; /* Empirical. */
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}
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static void
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nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
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int *burst, int *lwm)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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struct nv_fifo_info fifo_data;
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struct nv_sim_state sim_data;
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int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
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int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);
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uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1);
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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sim_data.pclk_khz = VClk;
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sim_data.mclk_khz = MClk;
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sim_data.nvclk_khz = NVClk;
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sim_data.bpp = bpp;
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sim_data.two_heads = nv_two_heads(dev);
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if ((pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||
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(pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {
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uint32_t type;
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int domain = pci_domain_nr(pdev->bus);
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pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1),
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0x7c, &type);
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sim_data.memory_type = (type >> 12) & 1;
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sim_data.memory_width = 64;
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sim_data.mem_latency = 3;
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sim_data.mem_page_miss = 10;
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} else {
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sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1;
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sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
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sim_data.mem_latency = cfg1 & 0xf;
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sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
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}
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if (drm->client.device.info.family == NV_DEVICE_INFO_V0_TNT)
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nv04_calc_arb(&fifo_data, &sim_data);
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else
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nv10_calc_arb(&fifo_data, &sim_data);
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*burst = ilog2(fifo_data.burst >> 4);
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*lwm = fifo_data.lwm >> 3;
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}
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static void
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nv20_update_arb(int *burst, int *lwm)
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{
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unsigned int fifo_size, burst_size, graphics_lwm;
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fifo_size = 2048;
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burst_size = 512;
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graphics_lwm = fifo_size - burst_size;
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*burst = ilog2(burst_size >> 5);
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*lwm = graphics_lwm >> 3;
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}
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void
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nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN)
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nv04_update_arb(dev, vclk, bpp, burst, lwm);
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else if ((pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
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(pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
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*burst = 128;
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*lwm = 0x0480;
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} else
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nv20_update_arb(burst, lwm);
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}
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