77 lines
1.5 KiB
C
77 lines
1.5 KiB
C
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/* SPDX-License-Identifier: MIT */
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#ifndef __NVBIOS_PLL_H__
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#define __NVBIOS_PLL_H__
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/*XXX: kill me */
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struct nvkm_pll_vals {
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union {
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struct {
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#ifdef __BIG_ENDIAN
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uint8_t N1, M1, N2, M2;
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#else
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uint8_t M1, N1, M2, N2;
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#endif
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};
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struct {
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uint16_t NM1, NM2;
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} __attribute__((packed));
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};
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int log2P;
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int refclk;
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};
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/* these match types in pll limits table version 0x40,
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* nvkm uses them on all chipsets internally where a
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* specific pll needs to be referenced, but the exact
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* register isn't known.
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*/
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enum nvbios_pll_type {
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PLL_CORE = 0x01,
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PLL_SHADER = 0x02,
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PLL_UNK03 = 0x03,
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PLL_MEMORY = 0x04,
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PLL_VDEC = 0x05,
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PLL_UNK40 = 0x40,
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PLL_UNK41 = 0x41,
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PLL_UNK42 = 0x42,
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PLL_VPLL0 = 0x80,
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PLL_VPLL1 = 0x81,
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PLL_VPLL2 = 0x82,
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PLL_VPLL3 = 0x83,
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PLL_MAX = 0xff
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};
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struct nvbios_pll {
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enum nvbios_pll_type type;
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u32 reg;
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u32 refclk;
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u8 min_p;
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u8 max_p;
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u8 bias_p;
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/*
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* for most pre nv50 cards setting a log2P of 7 (the common max_log2p
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* value) is no different to 6 (at least for vplls) so allowing the MNP
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* calc to use 7 causes the generated clock to be out by a factor of 2.
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* however, max_log2p cannot be fixed-up during parsing as the
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* unmodified max_log2p value is still needed for setting mplls, hence
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* an additional max_usable_log2p member
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*/
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u8 max_p_usable;
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struct {
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u32 min_freq;
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u32 max_freq;
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u32 min_inputfreq;
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u32 max_inputfreq;
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u8 min_m;
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u8 max_m;
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u8 min_n;
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u8 max_n;
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} vco1, vco2;
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};
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int nvbios_pll_parse(struct nvkm_bios *, u32 type, struct nvbios_pll *);
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#endif
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