141 lines
4.1 KiB
C
141 lines
4.1 KiB
C
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/*
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* Copyright 2019 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <core/firmware.h>
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#include <core/memory.h>
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#include <subdev/mmu.h>
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#include <subdev/pmu.h>
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#include <nvfw/acr.h>
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#include <nvfw/flcn.h>
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int
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gm20b_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size)
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{
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struct nvkm_subdev *subdev = &acr->subdev;
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acr->func->wpr_check(acr, &acr->wpr_start, &acr->wpr_end);
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if ((acr->wpr_end - acr->wpr_start) < wpr_size) {
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nvkm_error(subdev, "WPR image too big for WPR!\n");
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return -ENOSPC;
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}
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return nvkm_memory_new(subdev->device, NVKM_MEM_TARGET_INST,
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wpr_size, 0, true, &acr->wpr);
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}
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static int
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gm20b_acr_hsfw_load_bld(struct nvkm_falcon_fw *fw)
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{
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struct flcn_bl_dmem_desc hsdesc = {
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.ctx_dma = FALCON_DMAIDX_VIRT,
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.code_dma_base = fw->vma->addr >> 8,
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.non_sec_code_off = fw->nmem_base,
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.non_sec_code_size = fw->nmem_size,
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.sec_code_off = fw->imem_base,
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.sec_code_size = fw->imem_size,
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.code_entry_point = 0,
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.data_dma_base = (fw->vma->addr + fw->dmem_base_img) >> 8,
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.data_size = fw->dmem_size,
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};
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flcn_bl_dmem_desc_dump(fw->falcon->user, &hsdesc);
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return nvkm_falcon_pio_wr(fw->falcon, (u8 *)&hsdesc, 0, 0, DMEM, 0, sizeof(hsdesc), 0, 0);
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}
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static int
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gm20b_acr_load_setup(struct nvkm_falcon_fw *fw)
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{
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struct flcn_acr_desc *desc = (void *)&fw->fw.img[fw->dmem_base_img];
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struct nvkm_acr *acr = fw->falcon->owner->device->acr;
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desc->ucode_blob_base = nvkm_memory_addr(acr->wpr);
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desc->ucode_blob_size = nvkm_memory_size(acr->wpr);
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flcn_acr_desc_dump(&acr->subdev, desc);
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return 0;
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}
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const struct nvkm_falcon_fw_func
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gm20b_acr_load_0 = {
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.signature = gm200_flcn_fw_signature,
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.reset = gm200_flcn_fw_reset,
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.setup = gm20b_acr_load_setup,
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.load = gm200_flcn_fw_load,
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.load_bld = gm20b_acr_hsfw_load_bld,
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.boot = gm200_flcn_fw_boot,
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};
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
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MODULE_FIRMWARE("nvidia/gm20b/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gm20b/acr/ucode_load.bin");
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#endif
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static const struct nvkm_acr_hsf_fwif
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gm20b_acr_load_fwif[] = {
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{ 0, gm200_acr_hsfw_ctor, &gm20b_acr_load_0, NVKM_ACR_HSF_PMU, 0, 0x10 },
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{}
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};
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static const struct nvkm_acr_func
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gm20b_acr = {
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.load = gm20b_acr_load_fwif,
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.wpr_parse = gm200_acr_wpr_parse,
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.wpr_layout = gm200_acr_wpr_layout,
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.wpr_alloc = gm20b_acr_wpr_alloc,
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.wpr_build = gm200_acr_wpr_build,
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.wpr_patch = gm200_acr_wpr_patch,
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.wpr_check = gm200_acr_wpr_check,
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.init = gm200_acr_init,
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};
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int
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gm20b_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)
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{
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struct nvkm_subdev *subdev = &acr->subdev;
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const struct nvkm_acr_hsf_fwif *hsfwif;
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hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad",
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acr, "acr/bl", "acr/ucode_load", "load");
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if (IS_ERR(hsfwif))
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return PTR_ERR(hsfwif);
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return 0;
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}
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static const struct nvkm_acr_fwif
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gm20b_acr_fwif[] = {
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{ 0, gm20b_acr_load, &gm20b_acr },
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{ -1, gm200_acr_nofw, &gm200_acr },
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{}
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};
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int
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gm20b_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_acr **pacr)
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{
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return nvkm_acr_new_(gm20b_acr_fwif, device, type, inst, pacr);
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}
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