289 lines
7.8 KiB
C
289 lines
7.8 KiB
C
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/*
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* Copyright 2019 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "priv.h"
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#include <core/firmware.h>
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#include <core/memory.h>
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#include <subdev/mmu.h>
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#include <engine/sec2.h>
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#include <nvfw/acr.h>
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#include <nvfw/flcn.h>
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int
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gp102_acr_wpr_patch(struct nvkm_acr *acr, s64 adjust)
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{
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struct wpr_header_v1 hdr;
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struct lsb_header_v1 lsb;
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struct nvkm_acr_lsfw *lsfw;
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u32 offset = 0;
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do {
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nvkm_robj(acr->wpr, offset, &hdr, sizeof(hdr));
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wpr_header_v1_dump(&acr->subdev, &hdr);
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list_for_each_entry(lsfw, &acr->lsfw, head) {
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if (lsfw->id != hdr.falcon_id)
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continue;
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nvkm_robj(acr->wpr, hdr.lsb_offset, &lsb, sizeof(lsb));
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lsb_header_v1_dump(&acr->subdev, &lsb);
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lsfw->func->bld_patch(acr, lsb.tail.bl_data_off, adjust);
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break;
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}
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offset += sizeof(hdr);
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} while (hdr.falcon_id != WPR_HEADER_V1_FALCON_ID_INVALID);
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return 0;
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}
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int
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gp102_acr_wpr_build_lsb(struct nvkm_acr *acr, struct nvkm_acr_lsfw *lsfw)
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{
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struct lsb_header_v1 hdr;
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if (WARN_ON(lsfw->sig->size != sizeof(hdr.signature)))
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return -EINVAL;
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memcpy(&hdr.signature, lsfw->sig->data, lsfw->sig->size);
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gm200_acr_wpr_build_lsb_tail(lsfw, &hdr.tail);
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nvkm_wobj(acr->wpr, lsfw->offset.lsb, &hdr, sizeof(hdr));
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return 0;
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}
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int
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gp102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos)
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{
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struct nvkm_acr_lsfw *lsfw;
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u32 offset = 0;
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int ret;
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/* Fill per-LSF structures. */
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list_for_each_entry(lsfw, &acr->lsfw, head) {
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struct lsf_signature_v1 *sig = (void *)lsfw->sig->data;
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struct wpr_header_v1 hdr = {
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.falcon_id = lsfw->id,
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.lsb_offset = lsfw->offset.lsb,
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.bootstrap_owner = NVKM_ACR_LSF_SEC2,
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.lazy_bootstrap = rtos && lsfw->id != rtos->id,
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.bin_version = sig->version,
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.status = WPR_HEADER_V1_STATUS_COPY,
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};
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/* Write WPR header. */
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nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr));
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offset += sizeof(hdr);
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/* Write LSB header. */
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ret = gp102_acr_wpr_build_lsb(acr, lsfw);
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if (ret)
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return ret;
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/* Write ucode image. */
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nvkm_wobj(acr->wpr, lsfw->offset.img,
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lsfw->img.data,
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lsfw->img.size);
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/* Write bootloader data. */
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lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw);
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}
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/* Finalise WPR. */
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nvkm_wo32(acr->wpr, offset, WPR_HEADER_V1_FALCON_ID_INVALID);
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return 0;
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}
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int
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gp102_acr_wpr_alloc(struct nvkm_acr *acr, u32 wpr_size)
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{
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int ret = nvkm_memory_new(acr->subdev.device, NVKM_MEM_TARGET_INST,
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ALIGN(wpr_size, 0x40000) << 1, 0x40000, true,
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&acr->wpr);
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if (ret)
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return ret;
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acr->shadow_start = nvkm_memory_addr(acr->wpr);
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acr->wpr_start = acr->shadow_start + (nvkm_memory_size(acr->wpr) >> 1);
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acr->wpr_end = acr->wpr_start + (nvkm_memory_size(acr->wpr) >> 1);
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return 0;
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}
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u32
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gp102_acr_wpr_layout(struct nvkm_acr *acr)
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{
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struct nvkm_acr_lsfw *lsfw;
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u32 wpr = 0;
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wpr += 11 /* MAX_LSF */ * sizeof(struct wpr_header_v1);
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wpr = ALIGN(wpr, 256);
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wpr += 0x100; /* Shared sub-WPR headers. */
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list_for_each_entry(lsfw, &acr->lsfw, head) {
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wpr = ALIGN(wpr, 256);
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lsfw->offset.lsb = wpr;
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wpr += sizeof(struct lsb_header_v1);
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wpr = ALIGN(wpr, 4096);
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lsfw->offset.img = wpr;
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wpr += lsfw->img.size;
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wpr = ALIGN(wpr, 256);
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lsfw->offset.bld = wpr;
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lsfw->bl_data_size = ALIGN(lsfw->func->bld_size, 256);
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wpr += lsfw->bl_data_size;
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}
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return wpr;
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}
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int
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gp102_acr_wpr_parse(struct nvkm_acr *acr)
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{
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const struct wpr_header_v1 *hdr = (void *)acr->wpr_fw->data;
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struct nvkm_acr_lsfw *lsfw;
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while (hdr->falcon_id != WPR_HEADER_V1_FALCON_ID_INVALID) {
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wpr_header_v1_dump(&acr->subdev, hdr);
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lsfw = nvkm_acr_lsfw_add(NULL, acr, NULL, (hdr++)->falcon_id);
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if (IS_ERR(lsfw))
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return PTR_ERR(lsfw);
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}
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return 0;
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}
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MODULE_FIRMWARE("nvidia/gp102/acr/unload_bl.bin");
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MODULE_FIRMWARE("nvidia/gp102/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/gp104/acr/unload_bl.bin");
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MODULE_FIRMWARE("nvidia/gp104/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/gp106/acr/unload_bl.bin");
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MODULE_FIRMWARE("nvidia/gp106/acr/ucode_unload.bin");
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MODULE_FIRMWARE("nvidia/gp107/acr/unload_bl.bin");
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MODULE_FIRMWARE("nvidia/gp107/acr/ucode_unload.bin");
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static const struct nvkm_acr_hsf_fwif
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gp102_acr_unload_fwif[] = {
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{ 0, gm200_acr_hsfw_ctor, &gm200_acr_unload_0, NVKM_ACR_HSF_PMU, 0x1d, 0x00000010 },
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{}
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};
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int
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gp102_acr_load_setup(struct nvkm_falcon_fw *fw)
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{
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struct flcn_acr_desc_v1 *desc = (void *)&fw->fw.img[fw->dmem_base_img];
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struct nvkm_acr *acr = fw->falcon->owner->device->acr;
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desc->wpr_region_id = 1;
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desc->regions.no_regions = 2;
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desc->regions.region_props[0].start_addr = acr->wpr_start >> 8;
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desc->regions.region_props[0].end_addr = acr->wpr_end >> 8;
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desc->regions.region_props[0].region_id = 1;
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desc->regions.region_props[0].read_mask = 0xf;
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desc->regions.region_props[0].write_mask = 0xc;
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desc->regions.region_props[0].client_mask = 0x2;
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desc->regions.region_props[0].shadow_mem_start_addr = acr->shadow_start >> 8;
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flcn_acr_desc_v1_dump(&acr->subdev, desc);
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return 0;
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}
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static const struct nvkm_falcon_fw_func
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gp102_acr_load_0 = {
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.signature = gm200_flcn_fw_signature,
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.reset = gm200_flcn_fw_reset,
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.setup = gp102_acr_load_setup,
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.load = gm200_flcn_fw_load,
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.load_bld = gm200_acr_hsfw_load_bld,
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.boot = gm200_flcn_fw_boot,
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};
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MODULE_FIRMWARE("nvidia/gp102/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gp102/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gp104/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gp104/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gp106/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gp106/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gp107/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gp107/acr/ucode_load.bin");
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static const struct nvkm_acr_hsf_fwif
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gp102_acr_load_fwif[] = {
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{ 0, gm200_acr_hsfw_ctor, &gp102_acr_load_0, NVKM_ACR_HSF_SEC2, 0, 0x00000010 },
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{}
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};
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static const struct nvkm_acr_func
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gp102_acr = {
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.load = gp102_acr_load_fwif,
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.unload = gp102_acr_unload_fwif,
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.wpr_parse = gp102_acr_wpr_parse,
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.wpr_layout = gp102_acr_wpr_layout,
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.wpr_alloc = gp102_acr_wpr_alloc,
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.wpr_build = gp102_acr_wpr_build,
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.wpr_patch = gp102_acr_wpr_patch,
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.wpr_check = gm200_acr_wpr_check,
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.init = gm200_acr_init,
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};
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int
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gp102_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif)
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{
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struct nvkm_subdev *subdev = &acr->subdev;
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const struct nvkm_acr_hsf_fwif *hsfwif;
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hsfwif = nvkm_firmware_load(subdev, fwif->func->load, "AcrLoad",
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acr, "acr/bl", "acr/ucode_load", "load");
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if (IS_ERR(hsfwif))
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return PTR_ERR(hsfwif);
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hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "AcrUnload",
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acr, "acr/unload_bl", "acr/ucode_unload",
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"unload");
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if (IS_ERR(hsfwif))
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return PTR_ERR(hsfwif);
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return 0;
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}
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static const struct nvkm_acr_fwif
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gp102_acr_fwif[] = {
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{ 0, gp102_acr_load, &gp102_acr },
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{ -1, gm200_acr_nofw, &gm200_acr },
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{}
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};
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int
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gp102_acr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_acr **pacr)
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{
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return nvkm_acr_new_(gp102_acr_fwif, device, type, inst, pacr);
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}
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