2023-08-30 17:31:07 +02:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Synopsys DesignWare I2C adapter driver.
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*
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* Based on the TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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* Copyright (C) 2009 Provigent Ltd.
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*/
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#include <linux/bits.h>
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#include <linux/compiler_types.h>
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#include <linux/completion.h>
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#include <linux/dev_printk.h>
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#include <linux/errno.h>
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
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I2C_FUNC_SMBUS_BYTE | \
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I2C_FUNC_SMBUS_BYTE_DATA | \
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I2C_FUNC_SMBUS_WORD_DATA | \
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I2C_FUNC_SMBUS_BLOCK_DATA | \
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I2C_FUNC_SMBUS_I2C_BLOCK)
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#define DW_IC_CON_MASTER BIT(0)
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#define DW_IC_CON_SPEED_STD (1 << 1)
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#define DW_IC_CON_SPEED_FAST (2 << 1)
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#define DW_IC_CON_SPEED_HIGH (3 << 1)
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#define DW_IC_CON_SPEED_MASK GENMASK(2, 1)
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#define DW_IC_CON_10BITADDR_SLAVE BIT(3)
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#define DW_IC_CON_10BITADDR_MASTER BIT(4)
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#define DW_IC_CON_RESTART_EN BIT(5)
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#define DW_IC_CON_SLAVE_DISABLE BIT(6)
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#define DW_IC_CON_STOP_DET_IFADDRESSED BIT(7)
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#define DW_IC_CON_TX_EMPTY_CTRL BIT(8)
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#define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9)
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#define DW_IC_CON_BUS_CLEAR_CTRL BIT(11)
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#define DW_IC_DATA_CMD_DAT GENMASK(7, 0)
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2023-10-24 12:59:35 +02:00
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#define DW_IC_DATA_CMD_FIRST_DATA_BYTE BIT(11)
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2023-08-30 17:31:07 +02:00
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/*
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* Registers offset
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*/
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#define DW_IC_CON 0x00
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#define DW_IC_TAR 0x04
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#define DW_IC_SAR 0x08
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#define DW_IC_DATA_CMD 0x10
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#define DW_IC_SS_SCL_HCNT 0x14
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#define DW_IC_SS_SCL_LCNT 0x18
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#define DW_IC_FS_SCL_HCNT 0x1c
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#define DW_IC_FS_SCL_LCNT 0x20
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#define DW_IC_HS_SCL_HCNT 0x24
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#define DW_IC_HS_SCL_LCNT 0x28
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#define DW_IC_INTR_STAT 0x2c
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#define DW_IC_INTR_MASK 0x30
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#define DW_IC_RAW_INTR_STAT 0x34
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#define DW_IC_RX_TL 0x38
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#define DW_IC_TX_TL 0x3c
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#define DW_IC_CLR_INTR 0x40
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#define DW_IC_CLR_RX_UNDER 0x44
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#define DW_IC_CLR_RX_OVER 0x48
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#define DW_IC_CLR_TX_OVER 0x4c
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#define DW_IC_CLR_RD_REQ 0x50
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#define DW_IC_CLR_TX_ABRT 0x54
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#define DW_IC_CLR_RX_DONE 0x58
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#define DW_IC_CLR_ACTIVITY 0x5c
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#define DW_IC_CLR_STOP_DET 0x60
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#define DW_IC_CLR_START_DET 0x64
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#define DW_IC_CLR_GEN_CALL 0x68
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#define DW_IC_ENABLE 0x6c
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#define DW_IC_STATUS 0x70
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#define DW_IC_TXFLR 0x74
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#define DW_IC_RXFLR 0x78
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#define DW_IC_SDA_HOLD 0x7c
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#define DW_IC_TX_ABRT_SOURCE 0x80
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#define DW_IC_ENABLE_STATUS 0x9c
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#define DW_IC_CLR_RESTART_DET 0xa8
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#define DW_IC_COMP_PARAM_1 0xf4
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#define DW_IC_COMP_VERSION 0xf8
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#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A /* "111*" == v1.11* */
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#define DW_IC_COMP_TYPE 0xfc
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#define DW_IC_COMP_TYPE_VALUE 0x44570140 /* "DW" + 0x0140 */
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#define DW_IC_INTR_RX_UNDER BIT(0)
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#define DW_IC_INTR_RX_OVER BIT(1)
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#define DW_IC_INTR_RX_FULL BIT(2)
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#define DW_IC_INTR_TX_OVER BIT(3)
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#define DW_IC_INTR_TX_EMPTY BIT(4)
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#define DW_IC_INTR_RD_REQ BIT(5)
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#define DW_IC_INTR_TX_ABRT BIT(6)
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#define DW_IC_INTR_RX_DONE BIT(7)
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#define DW_IC_INTR_ACTIVITY BIT(8)
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#define DW_IC_INTR_STOP_DET BIT(9)
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#define DW_IC_INTR_START_DET BIT(10)
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#define DW_IC_INTR_GEN_CALL BIT(11)
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#define DW_IC_INTR_RESTART_DET BIT(12)
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#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
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DW_IC_INTR_TX_ABRT | \
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DW_IC_INTR_STOP_DET)
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#define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \
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DW_IC_INTR_TX_EMPTY)
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#define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \
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DW_IC_INTR_RX_UNDER | \
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DW_IC_INTR_RD_REQ)
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#define DW_IC_STATUS_ACTIVITY BIT(0)
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#define DW_IC_STATUS_TFE BIT(2)
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#define DW_IC_STATUS_RFNE BIT(3)
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#define DW_IC_STATUS_MASTER_ACTIVITY BIT(5)
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#define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6)
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#define DW_IC_SDA_HOLD_RX_SHIFT 16
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#define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16)
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#define DW_IC_ERR_TX_ABRT 0x1
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#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
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#define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
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#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2)
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/*
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* Sofware status flags
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*/
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#define STATUS_ACTIVE BIT(0)
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#define STATUS_WRITE_IN_PROGRESS BIT(1)
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#define STATUS_READ_IN_PROGRESS BIT(2)
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#define STATUS_MASK GENMASK(2, 0)
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/*
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* operation modes
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*/
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#define DW_IC_MASTER 0
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#define DW_IC_SLAVE 1
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/*
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* Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
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*
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* Only expected abort codes are listed here
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* refer to the datasheet for the full list
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*/
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#define ABRT_7B_ADDR_NOACK 0
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#define ABRT_10ADDR1_NOACK 1
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#define ABRT_10ADDR2_NOACK 2
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#define ABRT_TXDATA_NOACK 3
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#define ABRT_GCALL_NOACK 4
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#define ABRT_GCALL_READ 5
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#define ABRT_SBYTE_ACKDET 7
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#define ABRT_SBYTE_NORSTRT 9
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#define ABRT_10B_RD_NORSTRT 10
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#define ABRT_MASTER_DIS 11
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#define ARB_LOST 12
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#define ABRT_SLAVE_FLUSH_TXFIFO 13
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#define ABRT_SLAVE_ARBLOST 14
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#define ABRT_SLAVE_RD_INTX 15
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#define DW_IC_TX_ABRT_7B_ADDR_NOACK BIT(ABRT_7B_ADDR_NOACK)
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#define DW_IC_TX_ABRT_10ADDR1_NOACK BIT(ABRT_10ADDR1_NOACK)
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#define DW_IC_TX_ABRT_10ADDR2_NOACK BIT(ABRT_10ADDR2_NOACK)
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#define DW_IC_TX_ABRT_TXDATA_NOACK BIT(ABRT_TXDATA_NOACK)
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#define DW_IC_TX_ABRT_GCALL_NOACK BIT(ABRT_GCALL_NOACK)
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#define DW_IC_TX_ABRT_GCALL_READ BIT(ABRT_GCALL_READ)
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#define DW_IC_TX_ABRT_SBYTE_ACKDET BIT(ABRT_SBYTE_ACKDET)
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#define DW_IC_TX_ABRT_SBYTE_NORSTRT BIT(ABRT_SBYTE_NORSTRT)
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#define DW_IC_TX_ABRT_10B_RD_NORSTRT BIT(ABRT_10B_RD_NORSTRT)
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#define DW_IC_TX_ABRT_MASTER_DIS BIT(ABRT_MASTER_DIS)
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#define DW_IC_TX_ARB_LOST BIT(ARB_LOST)
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#define DW_IC_RX_ABRT_SLAVE_RD_INTX BIT(ABRT_SLAVE_RD_INTX)
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#define DW_IC_RX_ABRT_SLAVE_ARBLOST BIT(ABRT_SLAVE_ARBLOST)
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#define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO BIT(ABRT_SLAVE_FLUSH_TXFIFO)
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#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
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DW_IC_TX_ABRT_10ADDR1_NOACK | \
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DW_IC_TX_ABRT_10ADDR2_NOACK | \
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DW_IC_TX_ABRT_TXDATA_NOACK | \
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DW_IC_TX_ABRT_GCALL_NOACK)
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struct clk;
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struct device;
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struct reset_control;
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/**
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* struct dw_i2c_dev - private i2c-designware data
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* @dev: driver model device node
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* @map: IO registers map
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* @sysmap: System controller registers map
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* @base: IO registers pointer
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* @ext: Extended IO registers pointer
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* @cmd_complete: tx completion indicator
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* @clk: input reference clock
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* @pclk: clock required to access the registers
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* @rst: optional reset for the controller
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* @slave: represent an I2C slave device
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* @get_clk_rate_khz: callback to retrieve IP specific bus speed
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* @cmd_err: run time hadware error code
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* @msgs: points to an array of messages currently being transferred
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* @msgs_num: the number of elements in msgs
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* @msg_write_idx: the element index of the current tx message in the msgs array
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* @tx_buf_len: the length of the current tx buffer
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* @tx_buf: the current tx buffer
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* @msg_read_idx: the element index of the current rx message in the msgs array
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* @rx_buf_len: the length of the current rx buffer
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* @rx_buf: the current rx buffer
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* @msg_err: error status of the current transfer
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* @status: i2c master status, one of STATUS_*
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* @abort_source: copy of the TX_ABRT_SOURCE register
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* @irq: interrupt number for the i2c master
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* @flags: platform specific flags like type of IO accessors or model
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* @adapter: i2c subsystem adapter node
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* @functionality: I2C_FUNC_* ORed bits to reflect what controller does support
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* @master_cfg: configuration for the master device
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* @slave_cfg: configuration for the slave device
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* @tx_fifo_depth: depth of the hardware tx fifo
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* @rx_fifo_depth: depth of the hardware rx fifo
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* @rx_outstanding: current master-rx elements in tx fifo
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* @timings: bus clock frequency, SDA hold and other timings
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* @sda_hold_time: SDA hold value
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* @ss_hcnt: standard speed HCNT value
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* @ss_lcnt: standard speed LCNT value
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* @fs_hcnt: fast speed HCNT value
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* @fs_lcnt: fast speed LCNT value
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* @fp_hcnt: fast plus HCNT value
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* @fp_lcnt: fast plus LCNT value
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* @hs_hcnt: high speed HCNT value
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* @hs_lcnt: high speed LCNT value
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* @acquire_lock: function to acquire a hardware lock on the bus
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* @release_lock: function to release a hardware lock on the bus
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* @semaphore_idx: Index of table with semaphore type attached to the bus. It's
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* -1 if there is no semaphore.
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* @shared_with_punit: true if this bus is shared with the SoCs PUNIT
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* @disable: function to disable the controller
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* @init: function to initialize the I2C hardware
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* @set_sda_hold_time: callback to retrieve IP specific SDA hold timing
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* @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
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* @rinfo: I²C GPIO recovery information
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*
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* HCNT and LCNT parameters can be used if the platform knows more accurate
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* values than the one computed based only on the input clock frequency.
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* Leave them to be %0 if not used.
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*/
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struct dw_i2c_dev {
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struct device *dev;
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struct regmap *map;
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struct regmap *sysmap;
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void __iomem *base;
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void __iomem *ext;
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struct completion cmd_complete;
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struct clk *clk;
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struct clk *pclk;
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struct reset_control *rst;
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struct i2c_client *slave;
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u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
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int cmd_err;
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struct i2c_msg *msgs;
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int msgs_num;
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int msg_write_idx;
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u32 tx_buf_len;
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u8 *tx_buf;
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int msg_read_idx;
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u32 rx_buf_len;
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u8 *rx_buf;
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int msg_err;
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unsigned int status;
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unsigned int abort_source;
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int irq;
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u32 flags;
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struct i2c_adapter adapter;
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u32 functionality;
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u32 master_cfg;
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u32 slave_cfg;
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unsigned int tx_fifo_depth;
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unsigned int rx_fifo_depth;
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int rx_outstanding;
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struct i2c_timings timings;
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u32 sda_hold_time;
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u16 ss_hcnt;
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u16 ss_lcnt;
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u16 fs_hcnt;
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u16 fs_lcnt;
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u16 fp_hcnt;
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u16 fp_lcnt;
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u16 hs_hcnt;
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u16 hs_lcnt;
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int (*acquire_lock)(void);
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void (*release_lock)(void);
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int semaphore_idx;
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|
bool shared_with_punit;
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void (*disable)(struct dw_i2c_dev *dev);
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int (*init)(struct dw_i2c_dev *dev);
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int (*set_sda_hold_time)(struct dw_i2c_dev *dev);
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int mode;
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struct i2c_bus_recovery_info rinfo;
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};
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#define ACCESS_INTR_MASK BIT(0)
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#define ACCESS_NO_IRQ_SUSPEND BIT(1)
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#define ARBITRATION_SEMAPHORE BIT(2)
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#define MODEL_MSCC_OCELOT BIT(8)
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|
#define MODEL_BAIKAL_BT1 BIT(9)
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|
#define MODEL_AMD_NAVI_GPU BIT(10)
|
2023-10-24 12:59:35 +02:00
|
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|
#define MODEL_WANGXUN_SP BIT(11)
|
2023-08-30 17:31:07 +02:00
|
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|
#define MODEL_MASK GENMASK(11, 8)
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|
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|
/*
|
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* Enable UCSI interrupt by writing 0xd at register
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|
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* offset 0x474 specified in hardware specification.
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*/
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|
#define AMD_UCSI_INTR_REG 0x474
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#define AMD_UCSI_INTR_EN 0xd
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|
2023-10-24 12:59:35 +02:00
|
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|
#define TXGBE_TX_FIFO_DEPTH 4
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|
#define TXGBE_RX_FIFO_DEPTH 0
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|
2023-08-30 17:31:07 +02:00
|
|
|
struct i2c_dw_semaphore_callbacks {
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|
|
|
int (*probe)(struct dw_i2c_dev *dev);
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|
|
|
void (*remove)(struct dw_i2c_dev *dev);
|
|
|
|
|
};
|
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|
|
int i2c_dw_init_regmap(struct dw_i2c_dev *dev);
|
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|
|
|
u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);
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|
|
|
u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset);
|
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|
|
|
int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev);
|
|
|
|
|
u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev);
|
|
|
|
|
int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare);
|
|
|
|
|
int i2c_dw_acquire_lock(struct dw_i2c_dev *dev);
|
|
|
|
|
void i2c_dw_release_lock(struct dw_i2c_dev *dev);
|
|
|
|
|
int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev);
|
|
|
|
|
int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev);
|
|
|
|
|
int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev);
|
|
|
|
|
u32 i2c_dw_func(struct i2c_adapter *adap);
|
|
|
|
|
void i2c_dw_disable(struct dw_i2c_dev *dev);
|
|
|
|
|
|
|
|
|
|
static inline void __i2c_dw_enable(struct dw_i2c_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
dev->status |= STATUS_ACTIVE;
|
|
|
|
|
regmap_write(dev->map, DW_IC_ENABLE, 1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
regmap_write(dev->map, DW_IC_ENABLE, 0);
|
|
|
|
|
dev->status &= ~STATUS_ACTIVE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __i2c_dw_disable(struct dw_i2c_dev *dev);
|
|
|
|
|
|
|
|
|
|
extern void i2c_dw_configure_master(struct dw_i2c_dev *dev);
|
|
|
|
|
extern int i2c_dw_probe_master(struct dw_i2c_dev *dev);
|
|
|
|
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE)
|
|
|
|
|
extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev);
|
|
|
|
|
extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev);
|
|
|
|
|
#else
|
|
|
|
|
static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { }
|
|
|
|
|
static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; }
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
static inline int i2c_dw_probe(struct dw_i2c_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
switch (dev->mode) {
|
|
|
|
|
case DW_IC_SLAVE:
|
|
|
|
|
return i2c_dw_probe_slave(dev);
|
|
|
|
|
case DW_IC_MASTER:
|
|
|
|
|
return i2c_dw_probe_master(dev);
|
|
|
|
|
default:
|
|
|
|
|
dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void i2c_dw_configure(struct dw_i2c_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
if (i2c_detect_slave_mode(dev->dev))
|
|
|
|
|
i2c_dw_configure_slave(dev);
|
|
|
|
|
else
|
|
|
|
|
i2c_dw_configure_master(dev);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
|
|
|
|
|
int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_AMDPSP)
|
|
|
|
|
int i2c_dw_amdpsp_probe_lock_support(struct dw_i2c_dev *dev);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
int i2c_dw_validate_speed(struct dw_i2c_dev *dev);
|
|
|
|
|
void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev);
|
|
|
|
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_ACPI)
|
|
|
|
|
int i2c_dw_acpi_configure(struct device *device);
|
|
|
|
|
#else
|
|
|
|
|
static inline int i2c_dw_acpi_configure(struct device *device) { return -ENODEV; }
|
|
|
|
|
#endif
|
