309 lines
8.7 KiB
C
309 lines
8.7 KiB
C
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2020, MIPI Alliance, Inc.
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*
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* Author: Nicolas Pitre <npitre@baylibre.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/i3c/master.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include "hci.h"
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#include "ext_caps.h"
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#include "xfer_mode_rate.h"
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/* Extended Capability Header */
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#define CAP_HEADER_LENGTH GENMASK(23, 8)
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#define CAP_HEADER_ID GENMASK(7, 0)
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static int hci_extcap_hardware_id(struct i3c_hci *hci, void __iomem *base)
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{
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hci->vendor_mipi_id = readl(base + 0x04);
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hci->vendor_version_id = readl(base + 0x08);
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hci->vendor_product_id = readl(base + 0x0c);
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dev_info(&hci->master.dev, "vendor MIPI ID: %#x\n", hci->vendor_mipi_id);
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dev_info(&hci->master.dev, "vendor version ID: %#x\n", hci->vendor_version_id);
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dev_info(&hci->master.dev, "vendor product ID: %#x\n", hci->vendor_product_id);
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/* ought to go in a table if this grows too much */
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switch (hci->vendor_mipi_id) {
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case MIPI_VENDOR_NXP:
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hci->quirks |= HCI_QUIRK_RAW_CCC;
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DBG("raw CCC quirks set");
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break;
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}
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return 0;
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}
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static int hci_extcap_master_config(struct i3c_hci *hci, void __iomem *base)
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{
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u32 master_config = readl(base + 0x04);
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unsigned int operation_mode = FIELD_GET(GENMASK(5, 4), master_config);
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static const char * const functionality[] = {
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"(unknown)", "master only", "target only",
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"primary/secondary master" };
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dev_info(&hci->master.dev, "operation mode: %s\n", functionality[operation_mode]);
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if (operation_mode & 0x1)
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return 0;
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dev_err(&hci->master.dev, "only master mode is currently supported\n");
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return -EOPNOTSUPP;
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}
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static int hci_extcap_multi_bus(struct i3c_hci *hci, void __iomem *base)
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{
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u32 bus_instance = readl(base + 0x04);
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unsigned int count = FIELD_GET(GENMASK(3, 0), bus_instance);
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dev_info(&hci->master.dev, "%d bus instances\n", count);
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return 0;
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}
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static int hci_extcap_xfer_modes(struct i3c_hci *hci, void __iomem *base)
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{
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u32 header = readl(base);
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u32 entries = FIELD_GET(CAP_HEADER_LENGTH, header) - 1;
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unsigned int index;
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dev_info(&hci->master.dev, "transfer mode table has %d entries\n",
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entries);
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base += 4; /* skip header */
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for (index = 0; index < entries; index++) {
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u32 mode_entry = readl(base);
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DBG("mode %d: 0x%08x", index, mode_entry);
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/* TODO: will be needed when I3C core does more than SDR */
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base += 4;
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}
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return 0;
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}
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static int hci_extcap_xfer_rates(struct i3c_hci *hci, void __iomem *base)
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{
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u32 header = readl(base);
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u32 entries = FIELD_GET(CAP_HEADER_LENGTH, header) - 1;
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u32 rate_entry;
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unsigned int index, rate, rate_id, mode_id;
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base += 4; /* skip header */
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dev_info(&hci->master.dev, "available data rates:\n");
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for (index = 0; index < entries; index++) {
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rate_entry = readl(base);
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DBG("entry %d: 0x%08x", index, rate_entry);
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rate = FIELD_GET(XFERRATE_ACTUAL_RATE_KHZ, rate_entry);
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rate_id = FIELD_GET(XFERRATE_RATE_ID, rate_entry);
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mode_id = FIELD_GET(XFERRATE_MODE_ID, rate_entry);
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dev_info(&hci->master.dev, "rate %d for %s = %d kHz\n",
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rate_id,
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mode_id == XFERRATE_MODE_I3C ? "I3C" :
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mode_id == XFERRATE_MODE_I2C ? "I2C" :
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"unknown mode",
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rate);
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base += 4;
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}
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return 0;
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}
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static int hci_extcap_auto_command(struct i3c_hci *hci, void __iomem *base)
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{
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u32 autocmd_ext_caps = readl(base + 0x04);
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unsigned int max_count = FIELD_GET(GENMASK(3, 0), autocmd_ext_caps);
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u32 autocmd_ext_config = readl(base + 0x08);
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unsigned int count = FIELD_GET(GENMASK(3, 0), autocmd_ext_config);
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dev_info(&hci->master.dev, "%d/%d active auto-command entries\n",
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count, max_count);
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/* remember auto-command register location for later use */
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hci->AUTOCMD_regs = base;
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return 0;
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}
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static int hci_extcap_debug(struct i3c_hci *hci, void __iomem *base)
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{
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dev_info(&hci->master.dev, "debug registers present\n");
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hci->DEBUG_regs = base;
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return 0;
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}
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static int hci_extcap_scheduled_cmd(struct i3c_hci *hci, void __iomem *base)
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{
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dev_info(&hci->master.dev, "scheduled commands available\n");
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/* hci->schedcmd_regs = base; */
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return 0;
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}
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static int hci_extcap_non_curr_master(struct i3c_hci *hci, void __iomem *base)
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{
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dev_info(&hci->master.dev, "Non-Current Master support available\n");
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/* hci->NCM_regs = base; */
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return 0;
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}
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static int hci_extcap_ccc_resp_conf(struct i3c_hci *hci, void __iomem *base)
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{
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dev_info(&hci->master.dev, "CCC Response Configuration available\n");
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return 0;
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}
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static int hci_extcap_global_DAT(struct i3c_hci *hci, void __iomem *base)
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{
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dev_info(&hci->master.dev, "Global DAT available\n");
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return 0;
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}
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static int hci_extcap_multilane(struct i3c_hci *hci, void __iomem *base)
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{
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dev_info(&hci->master.dev, "Master Multi-Lane support available\n");
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return 0;
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}
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static int hci_extcap_ncm_multilane(struct i3c_hci *hci, void __iomem *base)
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{
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dev_info(&hci->master.dev, "NCM Multi-Lane support available\n");
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return 0;
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}
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struct hci_ext_caps {
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u8 id;
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u16 min_length;
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int (*parser)(struct i3c_hci *hci, void __iomem *base);
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};
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#define EXT_CAP(_id, _highest_mandatory_reg_offset, _parser) \
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{ .id = (_id), .parser = (_parser), \
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.min_length = (_highest_mandatory_reg_offset)/4 + 1 }
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static const struct hci_ext_caps ext_capabilities[] = {
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EXT_CAP(0x01, 0x0c, hci_extcap_hardware_id),
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EXT_CAP(0x02, 0x04, hci_extcap_master_config),
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EXT_CAP(0x03, 0x04, hci_extcap_multi_bus),
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EXT_CAP(0x04, 0x24, hci_extcap_xfer_modes),
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EXT_CAP(0x05, 0x08, hci_extcap_auto_command),
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EXT_CAP(0x08, 0x40, hci_extcap_xfer_rates),
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EXT_CAP(0x0c, 0x10, hci_extcap_debug),
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EXT_CAP(0x0d, 0x0c, hci_extcap_scheduled_cmd),
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EXT_CAP(0x0e, 0x80, hci_extcap_non_curr_master), /* TODO confirm size */
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EXT_CAP(0x0f, 0x04, hci_extcap_ccc_resp_conf),
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EXT_CAP(0x10, 0x08, hci_extcap_global_DAT),
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EXT_CAP(0x9d, 0x04, hci_extcap_multilane),
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EXT_CAP(0x9e, 0x04, hci_extcap_ncm_multilane),
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};
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static int hci_extcap_vendor_NXP(struct i3c_hci *hci, void __iomem *base)
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{
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hci->vendor_data = (__force void *)base;
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dev_info(&hci->master.dev, "Build Date Info = %#x\n", readl(base + 1*4));
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/* reset the FPGA */
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writel(0xdeadbeef, base + 1*4);
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return 0;
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}
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struct hci_ext_cap_vendor_specific {
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u32 vendor;
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u8 cap;
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u16 min_length;
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int (*parser)(struct i3c_hci *hci, void __iomem *base);
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};
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#define EXT_CAP_VENDOR(_vendor, _cap, _highest_mandatory_reg_offset) \
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{ .vendor = (MIPI_VENDOR_##_vendor), .cap = (_cap), \
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.parser = (hci_extcap_vendor_##_vendor), \
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.min_length = (_highest_mandatory_reg_offset)/4 + 1 }
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static const struct hci_ext_cap_vendor_specific vendor_ext_caps[] = {
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EXT_CAP_VENDOR(NXP, 0xc0, 0x20),
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};
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static int hci_extcap_vendor_specific(struct i3c_hci *hci, void __iomem *base,
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u32 cap_id, u32 cap_length)
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{
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const struct hci_ext_cap_vendor_specific *vendor_cap_entry;
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int i;
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vendor_cap_entry = NULL;
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for (i = 0; i < ARRAY_SIZE(vendor_ext_caps); i++) {
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if (vendor_ext_caps[i].vendor == hci->vendor_mipi_id &&
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vendor_ext_caps[i].cap == cap_id) {
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vendor_cap_entry = &vendor_ext_caps[i];
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break;
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}
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}
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if (!vendor_cap_entry) {
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dev_notice(&hci->master.dev,
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"unknown ext_cap 0x%02x for vendor 0x%02x\n",
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cap_id, hci->vendor_mipi_id);
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return 0;
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}
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if (cap_length < vendor_cap_entry->min_length) {
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dev_err(&hci->master.dev,
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"ext_cap 0x%02x has size %d (expecting >= %d)\n",
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cap_id, cap_length, vendor_cap_entry->min_length);
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return -EINVAL;
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}
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return vendor_cap_entry->parser(hci, base);
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}
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int i3c_hci_parse_ext_caps(struct i3c_hci *hci)
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{
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void __iomem *curr_cap = hci->EXTCAPS_regs;
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void __iomem *end = curr_cap + 0x1000; /* some arbitrary limit */
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u32 cap_header, cap_id, cap_length;
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const struct hci_ext_caps *cap_entry;
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int i, err = 0;
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if (!curr_cap)
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return 0;
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for (; !err && curr_cap < end; curr_cap += cap_length * 4) {
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cap_header = readl(curr_cap);
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cap_id = FIELD_GET(CAP_HEADER_ID, cap_header);
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cap_length = FIELD_GET(CAP_HEADER_LENGTH, cap_header);
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DBG("id=0x%02x length=%d", cap_id, cap_length);
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if (!cap_length)
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break;
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if (curr_cap + cap_length * 4 >= end) {
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dev_err(&hci->master.dev,
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"ext_cap 0x%02x has size %d (too big)\n",
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cap_id, cap_length);
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err = -EINVAL;
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break;
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}
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if (cap_id >= 0xc0 && cap_id <= 0xcf) {
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err = hci_extcap_vendor_specific(hci, curr_cap,
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cap_id, cap_length);
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continue;
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}
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cap_entry = NULL;
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for (i = 0; i < ARRAY_SIZE(ext_capabilities); i++) {
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if (ext_capabilities[i].id == cap_id) {
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cap_entry = &ext_capabilities[i];
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break;
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}
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}
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if (!cap_entry) {
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dev_notice(&hci->master.dev,
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"unknown ext_cap 0x%02x\n", cap_id);
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} else if (cap_length < cap_entry->min_length) {
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dev_err(&hci->master.dev,
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"ext_cap 0x%02x has size %d (expecting >= %d)\n",
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cap_id, cap_length, cap_entry->min_length);
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err = -EINVAL;
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} else {
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err = cap_entry->parser(hci, curr_cap);
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}
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}
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return err;
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}
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