48 lines
1.6 KiB
C
48 lines
1.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MDP_REG_WDMA_H__
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#define __MDP_REG_WDMA_H__
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#define WDMA_EN 0x008
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#define WDMA_RST 0x00c
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#define WDMA_CFG 0x014
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#define WDMA_SRC_SIZE 0x018
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#define WDMA_CLIP_SIZE 0x01c
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#define WDMA_CLIP_COORD 0x020
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#define WDMA_DST_W_IN_BYTE 0x028
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#define WDMA_ALPHA 0x02c
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#define WDMA_BUF_CON2 0x03c
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#define WDMA_DST_UV_PITCH 0x078
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#define WDMA_DST_ADDR_OFFSET 0x080
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#define WDMA_DST_U_ADDR_OFFSET 0x084
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#define WDMA_DST_V_ADDR_OFFSET 0x088
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#define WDMA_FLOW_CTRL_DBG 0x0a0
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#define WDMA_DST_ADDR 0xf00
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#define WDMA_DST_U_ADDR 0xf04
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#define WDMA_DST_V_ADDR 0xf08
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/* MASK */
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#define WDMA_EN_MASK 0x00000001
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#define WDMA_RST_MASK 0x00000001
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#define WDMA_CFG_MASK 0xff03bff0
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#define WDMA_SRC_SIZE_MASK 0x3fff3fff
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#define WDMA_CLIP_SIZE_MASK 0x3fff3fff
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#define WDMA_CLIP_COORD_MASK 0x3fff3fff
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#define WDMA_DST_W_IN_BYTE_MASK 0x0000ffff
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#define WDMA_ALPHA_MASK 0x800000ff
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#define WDMA_BUF_CON2_MASK 0xffffffff
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#define WDMA_DST_UV_PITCH_MASK 0x0000ffff
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#define WDMA_DST_ADDR_OFFSET_MASK 0x0fffffff
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#define WDMA_DST_U_ADDR_OFFSET_MASK 0x0fffffff
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#define WDMA_DST_V_ADDR_OFFSET_MASK 0x0fffffff
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#define WDMA_FLOW_CTRL_DBG_MASK 0x0000f3ff
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#define WDMA_DST_ADDR_MASK 0xffffffff
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#define WDMA_DST_U_ADDR_MASK 0xffffffff
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#define WDMA_DST_V_ADDR_MASK 0xffffffff
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#endif // __MDP_REG_WDMA_H__
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