341 lines
8.4 KiB
C
341 lines
8.4 KiB
C
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/*
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* Driver for MMC and SSD cards for Cavium OCTEON SOCs.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012-2017 Cavium Inc.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/gpio/consumer.h>
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#include <linux/interrupt.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <asm/octeon/octeon.h>
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#include "cavium.h"
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#define CVMX_MIO_BOOT_CTL CVMX_ADD_IO_SEG(0x00011800000000D0ull)
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/*
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* The l2c* functions below are used for the EMMC-17978 workaround.
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*
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* Due to a bug in the design of the MMC bus hardware, the 2nd to last
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* cache block of a DMA read must be locked into the L2 Cache.
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* Otherwise, data corruption may occur.
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*/
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static inline void *phys_to_ptr(u64 address)
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{
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return (void *)(address | (1ull << 63)); /* XKPHYS */
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}
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/*
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* Lock a single line into L2. The line is zeroed before locking
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* to make sure no dram accesses are made.
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*/
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static void l2c_lock_line(u64 addr)
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{
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char *addr_ptr = phys_to_ptr(addr);
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asm volatile (
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"cache 31, %[line]" /* Unlock the line */
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::[line] "m" (*addr_ptr));
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}
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/* Unlock a single line in the L2 cache. */
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static void l2c_unlock_line(u64 addr)
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{
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char *addr_ptr = phys_to_ptr(addr);
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asm volatile (
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"cache 23, %[line]" /* Unlock the line */
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::[line] "m" (*addr_ptr));
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}
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/* Locks a memory region in the L2 cache. */
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static void l2c_lock_mem_region(u64 start, u64 len)
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{
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u64 end;
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/* Round start/end to cache line boundaries */
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end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE);
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start = ALIGN(start, CVMX_CACHE_LINE_SIZE);
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while (start <= end) {
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l2c_lock_line(start);
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start += CVMX_CACHE_LINE_SIZE;
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}
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asm volatile("sync");
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}
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/* Unlock a memory region in the L2 cache. */
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static void l2c_unlock_mem_region(u64 start, u64 len)
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{
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u64 end;
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/* Round start/end to cache line boundaries */
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end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE);
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start = ALIGN(start, CVMX_CACHE_LINE_SIZE);
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while (start <= end) {
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l2c_unlock_line(start);
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start += CVMX_CACHE_LINE_SIZE;
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}
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}
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static void octeon_mmc_acquire_bus(struct cvm_mmc_host *host)
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{
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if (!host->has_ciu3) {
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down(&octeon_bootbus_sem);
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/* For CN70XX, switch the MMC controller onto the bus. */
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if (OCTEON_IS_MODEL(OCTEON_CN70XX))
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writeq(0, (void __iomem *)CVMX_MIO_BOOT_CTL);
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} else {
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down(&host->mmc_serializer);
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}
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}
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static void octeon_mmc_release_bus(struct cvm_mmc_host *host)
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{
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if (!host->has_ciu3)
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up(&octeon_bootbus_sem);
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else
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up(&host->mmc_serializer);
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}
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static void octeon_mmc_int_enable(struct cvm_mmc_host *host, u64 val)
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{
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writeq(val, host->base + MIO_EMM_INT(host));
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if (!host->has_ciu3)
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writeq(val, host->base + MIO_EMM_INT_EN(host));
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}
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static void octeon_mmc_set_shared_power(struct cvm_mmc_host *host, int dir)
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{
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if (dir == 0)
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if (!atomic_dec_return(&host->shared_power_users))
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gpiod_set_value_cansleep(host->global_pwr_gpiod, 0);
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if (dir == 1)
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if (atomic_inc_return(&host->shared_power_users) == 1)
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gpiod_set_value_cansleep(host->global_pwr_gpiod, 1);
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}
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static void octeon_mmc_dmar_fixup(struct cvm_mmc_host *host,
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struct mmc_command *cmd,
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struct mmc_data *data,
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u64 addr)
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{
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if (cmd->opcode != MMC_WRITE_MULTIPLE_BLOCK)
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return;
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if (data->blksz * data->blocks <= 1024)
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return;
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host->n_minus_one = addr + (data->blksz * data->blocks) - 1024;
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l2c_lock_mem_region(host->n_minus_one, 512);
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}
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static void octeon_mmc_dmar_fixup_done(struct cvm_mmc_host *host)
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{
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if (!host->n_minus_one)
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return;
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l2c_unlock_mem_region(host->n_minus_one, 512);
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host->n_minus_one = 0;
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}
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static int octeon_mmc_probe(struct platform_device *pdev)
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{
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struct device_node *cn, *node = pdev->dev.of_node;
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struct cvm_mmc_host *host;
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void __iomem *base;
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int mmc_irq[9];
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int i, ret = 0;
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u64 val;
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host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
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if (!host)
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return -ENOMEM;
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spin_lock_init(&host->irq_handler_lock);
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sema_init(&host->mmc_serializer, 1);
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host->dev = &pdev->dev;
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host->acquire_bus = octeon_mmc_acquire_bus;
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host->release_bus = octeon_mmc_release_bus;
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host->int_enable = octeon_mmc_int_enable;
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host->set_shared_power = octeon_mmc_set_shared_power;
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
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OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
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host->dmar_fixup = octeon_mmc_dmar_fixup;
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host->dmar_fixup_done = octeon_mmc_dmar_fixup_done;
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}
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host->sys_freq = octeon_get_io_clock_rate();
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if (of_device_is_compatible(node, "cavium,octeon-7890-mmc")) {
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host->big_dma_addr = true;
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host->need_irq_handler_lock = true;
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host->has_ciu3 = true;
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host->use_sg = true;
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/*
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* First seven are the EMM_INT bits 0..6, then two for
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* the EMM_DMA_INT bits
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*/
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for (i = 0; i < 9; i++) {
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mmc_irq[i] = platform_get_irq(pdev, i);
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if (mmc_irq[i] < 0)
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return mmc_irq[i];
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/* work around legacy u-boot device trees */
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irq_set_irq_type(mmc_irq[i], IRQ_TYPE_EDGE_RISING);
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}
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} else {
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host->big_dma_addr = false;
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host->need_irq_handler_lock = false;
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host->has_ciu3 = false;
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/* First one is EMM second DMA */
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for (i = 0; i < 2; i++) {
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mmc_irq[i] = platform_get_irq(pdev, i);
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if (mmc_irq[i] < 0)
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return mmc_irq[i];
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}
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}
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host->last_slot = -1;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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host->base = base;
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host->reg_off = 0;
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base = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(base))
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return PTR_ERR(base);
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host->dma_base = base;
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/*
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* To keep the register addresses shared we intentionaly use
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* a negative offset here, first register used on Octeon therefore
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* starts at 0x20 (MIO_EMM_DMA_CFG).
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*/
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host->reg_off_dma = -0x20;
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ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
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if (ret)
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return ret;
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/*
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* Clear out any pending interrupts that may be left over from
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* bootloader.
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*/
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val = readq(host->base + MIO_EMM_INT(host));
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writeq(val, host->base + MIO_EMM_INT(host));
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if (host->has_ciu3) {
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/* Only CMD_DONE, DMA_DONE, CMD_ERR, DMA_ERR */
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for (i = 1; i <= 4; i++) {
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ret = devm_request_irq(&pdev->dev, mmc_irq[i],
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cvm_mmc_interrupt,
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0, cvm_mmc_irq_names[i], host);
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if (ret < 0) {
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dev_err(&pdev->dev, "Error: devm_request_irq %d\n",
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mmc_irq[i]);
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return ret;
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}
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}
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} else {
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ret = devm_request_irq(&pdev->dev, mmc_irq[0],
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cvm_mmc_interrupt, 0, KBUILD_MODNAME,
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host);
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if (ret < 0) {
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dev_err(&pdev->dev, "Error: devm_request_irq %d\n",
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mmc_irq[0]);
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return ret;
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}
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}
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host->global_pwr_gpiod = devm_gpiod_get_optional(&pdev->dev,
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"power",
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GPIOD_OUT_HIGH);
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if (IS_ERR(host->global_pwr_gpiod)) {
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dev_err(&pdev->dev, "Invalid power GPIO\n");
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return PTR_ERR(host->global_pwr_gpiod);
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}
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platform_set_drvdata(pdev, host);
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i = 0;
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for_each_child_of_node(node, cn) {
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host->slot_pdev[i] =
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of_platform_device_create(cn, NULL, &pdev->dev);
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if (!host->slot_pdev[i]) {
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i++;
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continue;
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}
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ret = cvm_mmc_of_slot_probe(&host->slot_pdev[i]->dev, host);
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if (ret) {
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dev_err(&pdev->dev, "Error populating slots\n");
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octeon_mmc_set_shared_power(host, 0);
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of_node_put(cn);
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goto error;
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}
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i++;
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}
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return 0;
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error:
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for (i = 0; i < CAVIUM_MAX_MMC; i++) {
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if (host->slot[i])
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cvm_mmc_of_slot_remove(host->slot[i]);
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if (host->slot_pdev[i])
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of_platform_device_destroy(&host->slot_pdev[i]->dev, NULL);
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}
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return ret;
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}
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static int octeon_mmc_remove(struct platform_device *pdev)
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{
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struct cvm_mmc_host *host = platform_get_drvdata(pdev);
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u64 dma_cfg;
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int i;
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for (i = 0; i < CAVIUM_MAX_MMC; i++)
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if (host->slot[i])
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cvm_mmc_of_slot_remove(host->slot[i]);
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dma_cfg = readq(host->dma_base + MIO_EMM_DMA_CFG(host));
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dma_cfg &= ~MIO_EMM_DMA_CFG_EN;
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writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host));
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octeon_mmc_set_shared_power(host, 0);
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return 0;
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}
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static const struct of_device_id octeon_mmc_match[] = {
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{
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.compatible = "cavium,octeon-6130-mmc",
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},
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{
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.compatible = "cavium,octeon-7890-mmc",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, octeon_mmc_match);
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static struct platform_driver octeon_mmc_driver = {
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.probe = octeon_mmc_probe,
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.remove = octeon_mmc_remove,
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.driver = {
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.name = KBUILD_MODNAME,
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.probe_type = PROBE_PREFER_ASYNCHRONOUS,
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.of_match_table = octeon_mmc_match,
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},
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};
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module_platform_driver(octeon_mmc_driver);
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MODULE_AUTHOR("Cavium Inc. <support@cavium.com>");
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MODULE_DESCRIPTION("Low-level driver for Cavium OCTEON MMC/SSD card");
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MODULE_LICENSE("GPL");
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