443 lines
13 KiB
C
443 lines
13 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (C) 2014 Broadcom Corporation
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/*
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* iProc SDHCI platform driver
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*/
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#include <linux/acpi.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/mmc/host.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include "sdhci-pltfm.h"
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struct sdhci_iproc_data {
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const struct sdhci_pltfm_data *pdata;
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u32 caps;
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u32 caps1;
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u32 mmc_caps;
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bool missing_caps;
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};
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struct sdhci_iproc_host {
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const struct sdhci_iproc_data *data;
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u32 shadow_cmd;
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u32 shadow_blk;
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bool is_cmd_shadowed;
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bool is_blk_shadowed;
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};
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#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
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static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
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{
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u32 val = readl(host->ioaddr + reg);
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pr_debug("%s: readl [0x%02x] 0x%08x\n",
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mmc_hostname(host->mmc), reg, val);
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return val;
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}
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static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
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u32 val;
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u16 word;
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if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) {
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/* Get the saved transfer mode */
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val = iproc_host->shadow_cmd;
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} else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
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iproc_host->is_blk_shadowed) {
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/* Get the saved block info */
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val = iproc_host->shadow_blk;
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} else {
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val = sdhci_iproc_readl(host, (reg & ~3));
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}
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word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
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return word;
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}
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static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
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{
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u32 val = sdhci_iproc_readl(host, (reg & ~3));
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u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
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return byte;
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}
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static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
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{
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pr_debug("%s: writel [0x%02x] 0x%08x\n",
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mmc_hostname(host->mmc), reg, val);
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writel(val, host->ioaddr + reg);
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if (host->clock <= 400000) {
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/* Round up to micro-second four SD clock delay */
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if (host->clock)
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udelay((4 * 1000000 + host->clock - 1) / host->clock);
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else
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udelay(10);
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}
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}
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/*
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* The Arasan has a bugette whereby it may lose the content of successive
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* writes to the same register that are within two SD-card clock cycles of
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* each other (a clock domain crossing problem). The data
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* register does not have this problem, which is just as well - otherwise we'd
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* have to nobble the DMA engine too.
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*
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* This wouldn't be a problem with the code except that we can only write the
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* controller with 32-bit writes. So two different 16-bit registers are
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* written back to back creates the problem.
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*
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* In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
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* are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
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* The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
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* the work around can be further optimized. We can keep shadow values of
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* BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
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* Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
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* by the TRANSFER+COMMAND in another 32-bit write.
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*/
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static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
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u32 word_shift = REG_OFFSET_IN_BITS(reg);
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u32 mask = 0xffff << word_shift;
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u32 oldval, newval;
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if (reg == SDHCI_COMMAND) {
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/* Write the block now as we are issuing a command */
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if (iproc_host->is_blk_shadowed) {
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sdhci_iproc_writel(host, iproc_host->shadow_blk,
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SDHCI_BLOCK_SIZE);
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iproc_host->is_blk_shadowed = false;
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}
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oldval = iproc_host->shadow_cmd;
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iproc_host->is_cmd_shadowed = false;
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} else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
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iproc_host->is_blk_shadowed) {
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/* Block size and count are stored in shadow reg */
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oldval = iproc_host->shadow_blk;
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} else {
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/* Read reg, all other registers are not shadowed */
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oldval = sdhci_iproc_readl(host, (reg & ~3));
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}
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newval = (oldval & ~mask) | (val << word_shift);
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if (reg == SDHCI_TRANSFER_MODE) {
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/* Save the transfer mode until the command is issued */
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iproc_host->shadow_cmd = newval;
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iproc_host->is_cmd_shadowed = true;
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} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
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/* Save the block info until the command is issued */
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iproc_host->shadow_blk = newval;
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iproc_host->is_blk_shadowed = true;
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} else {
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/* Command or other regular 32-bit write */
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sdhci_iproc_writel(host, newval, reg & ~3);
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}
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}
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static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
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u32 byte_shift = REG_OFFSET_IN_BITS(reg);
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u32 mask = 0xff << byte_shift;
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u32 newval = (oldval & ~mask) | (val << byte_shift);
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sdhci_iproc_writel(host, newval, reg & ~3);
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}
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static unsigned int sdhci_iproc_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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if (pltfm_host->clk)
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return sdhci_pltfm_clk_get_max_clock(host);
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else
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return pltfm_host->clock;
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}
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/*
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* There is a known bug on BCM2711's SDHCI core integration where the
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* controller will hang when the difference between the core clock and the bus
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* clock is too great. Specifically this can be reproduced under the following
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* conditions:
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*
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* - No SD card plugged in, polling thread is running, probing cards at
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* 100 kHz.
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* - BCM2711's core clock configured at 500MHz or more
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*
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* So we set 200kHz as the minimum clock frequency available for that SoC.
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*/
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static unsigned int sdhci_iproc_bcm2711_get_min_clock(struct sdhci_host *host)
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{
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return 200000;
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}
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static const struct sdhci_ops sdhci_iproc_ops = {
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.set_clock = sdhci_set_clock,
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.get_max_clock = sdhci_iproc_get_max_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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static const struct sdhci_ops sdhci_iproc_32only_ops = {
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.read_l = sdhci_iproc_readl,
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.read_w = sdhci_iproc_readw,
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.read_b = sdhci_iproc_readb,
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.write_l = sdhci_iproc_writel,
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.write_w = sdhci_iproc_writew,
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.write_b = sdhci_iproc_writeb,
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.set_clock = sdhci_set_clock,
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.get_max_clock = sdhci_iproc_get_max_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
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.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_NO_HISPD_BIT,
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.quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | SDHCI_QUIRK2_HOST_OFF_CARD_ON,
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.ops = &sdhci_iproc_32only_ops,
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};
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static const struct sdhci_iproc_data iproc_cygnus_data = {
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.pdata = &sdhci_iproc_cygnus_pltfm_data,
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.caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
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& SDHCI_MAX_BLOCK_MASK) |
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SDHCI_CAN_VDD_330 |
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SDHCI_CAN_VDD_180 |
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SDHCI_CAN_DO_SUSPEND |
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SDHCI_CAN_DO_HISPD |
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SDHCI_CAN_DO_ADMA2 |
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SDHCI_CAN_DO_SDMA,
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.caps1 = SDHCI_DRIVER_TYPE_C |
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SDHCI_DRIVER_TYPE_D |
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SDHCI_SUPPORT_DDR50,
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.mmc_caps = MMC_CAP_1_8V_DDR,
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};
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static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
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.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |
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SDHCI_QUIRK_NO_HISPD_BIT,
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.quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
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.ops = &sdhci_iproc_ops,
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};
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static const struct sdhci_iproc_data iproc_data = {
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.pdata = &sdhci_iproc_pltfm_data,
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.caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
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& SDHCI_MAX_BLOCK_MASK) |
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SDHCI_CAN_VDD_330 |
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SDHCI_CAN_VDD_180 |
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SDHCI_CAN_DO_SUSPEND |
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SDHCI_CAN_DO_HISPD |
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SDHCI_CAN_DO_ADMA2 |
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SDHCI_CAN_DO_SDMA,
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.caps1 = SDHCI_DRIVER_TYPE_C |
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SDHCI_DRIVER_TYPE_D |
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SDHCI_SUPPORT_DDR50,
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};
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static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = {
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.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_NO_HISPD_BIT,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
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.ops = &sdhci_iproc_32only_ops,
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};
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static const struct sdhci_iproc_data bcm2835_data = {
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.pdata = &sdhci_bcm2835_pltfm_data,
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.caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
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& SDHCI_MAX_BLOCK_MASK) |
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SDHCI_CAN_VDD_330 |
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SDHCI_CAN_DO_HISPD,
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.caps1 = SDHCI_DRIVER_TYPE_A |
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SDHCI_DRIVER_TYPE_C,
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.mmc_caps = 0x00000000,
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.missing_caps = true,
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};
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static const struct sdhci_ops sdhci_iproc_bcm2711_ops = {
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.read_l = sdhci_iproc_readl,
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.read_w = sdhci_iproc_readw,
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.read_b = sdhci_iproc_readb,
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.write_l = sdhci_iproc_writel,
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.write_w = sdhci_iproc_writew,
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.write_b = sdhci_iproc_writeb,
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.set_clock = sdhci_set_clock,
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.set_power = sdhci_set_power_and_bus_voltage,
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.get_max_clock = sdhci_iproc_get_max_clock,
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.get_min_clock = sdhci_iproc_bcm2711_get_min_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
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.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
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.ops = &sdhci_iproc_bcm2711_ops,
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};
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static const struct sdhci_iproc_data bcm2711_data = {
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.pdata = &sdhci_bcm2711_pltfm_data,
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.mmc_caps = MMC_CAP_3_3V_DDR,
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};
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static const struct sdhci_pltfm_data sdhci_bcm7211a0_pltfm_data = {
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.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
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SDHCI_QUIRK_BROKEN_DMA |
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SDHCI_QUIRK_BROKEN_ADMA,
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.ops = &sdhci_iproc_ops,
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};
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#define BCM7211A0_BASE_CLK_MHZ 100
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static const struct sdhci_iproc_data bcm7211a0_data = {
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.pdata = &sdhci_bcm7211a0_pltfm_data,
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.caps = ((BCM7211A0_BASE_CLK_MHZ / 2) << SDHCI_TIMEOUT_CLK_SHIFT) |
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(BCM7211A0_BASE_CLK_MHZ << SDHCI_CLOCK_BASE_SHIFT) |
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((0x2 << SDHCI_MAX_BLOCK_SHIFT)
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& SDHCI_MAX_BLOCK_MASK) |
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SDHCI_CAN_VDD_330 |
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SDHCI_CAN_VDD_180 |
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SDHCI_CAN_DO_SUSPEND |
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SDHCI_CAN_DO_HISPD,
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.caps1 = SDHCI_DRIVER_TYPE_C |
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SDHCI_DRIVER_TYPE_D,
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.missing_caps = true,
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};
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static const struct of_device_id sdhci_iproc_of_match[] = {
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{ .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
|
||
|
|
{ .compatible = "brcm,bcm2711-emmc2", .data = &bcm2711_data },
|
||
|
|
{ .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
|
||
|
|
{ .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
|
||
|
|
{ .compatible = "brcm,bcm7211a0-sdhci", .data = &bcm7211a0_data },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
|
||
|
|
|
||
|
|
#ifdef CONFIG_ACPI
|
||
|
|
/*
|
||
|
|
* This is a duplicate of bcm2835_(pltfrm_)data without caps quirks
|
||
|
|
* which are provided by the ACPI table.
|
||
|
|
*/
|
||
|
|
static const struct sdhci_pltfm_data sdhci_bcm_arasan_data = {
|
||
|
|
.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
|
||
|
|
SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
|
||
|
|
SDHCI_QUIRK_NO_HISPD_BIT,
|
||
|
|
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
|
||
|
|
.ops = &sdhci_iproc_32only_ops,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct sdhci_iproc_data bcm_arasan_data = {
|
||
|
|
.pdata = &sdhci_bcm_arasan_data,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct acpi_device_id sdhci_iproc_acpi_ids[] = {
|
||
|
|
{ .id = "BRCM5871", .driver_data = (kernel_ulong_t)&iproc_cygnus_data },
|
||
|
|
{ .id = "BRCM5872", .driver_data = (kernel_ulong_t)&iproc_data },
|
||
|
|
{ .id = "BCM2847", .driver_data = (kernel_ulong_t)&bcm_arasan_data },
|
||
|
|
{ .id = "BRCME88C", .driver_data = (kernel_ulong_t)&bcm2711_data },
|
||
|
|
{ /* sentinel */ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(acpi, sdhci_iproc_acpi_ids);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static int sdhci_iproc_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct device *dev = &pdev->dev;
|
||
|
|
const struct sdhci_iproc_data *iproc_data = NULL;
|
||
|
|
struct sdhci_host *host;
|
||
|
|
struct sdhci_iproc_host *iproc_host;
|
||
|
|
struct sdhci_pltfm_host *pltfm_host;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
iproc_data = device_get_match_data(dev);
|
||
|
|
if (!iproc_data)
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
|
||
|
|
if (IS_ERR(host))
|
||
|
|
return PTR_ERR(host);
|
||
|
|
|
||
|
|
pltfm_host = sdhci_priv(host);
|
||
|
|
iproc_host = sdhci_pltfm_priv(pltfm_host);
|
||
|
|
|
||
|
|
iproc_host->data = iproc_data;
|
||
|
|
|
||
|
|
ret = mmc_of_parse(host->mmc);
|
||
|
|
if (ret)
|
||
|
|
goto err;
|
||
|
|
|
||
|
|
sdhci_get_property(pdev);
|
||
|
|
|
||
|
|
host->mmc->caps |= iproc_host->data->mmc_caps;
|
||
|
|
|
||
|
|
if (dev->of_node) {
|
||
|
|
pltfm_host->clk = devm_clk_get(dev, NULL);
|
||
|
|
if (IS_ERR(pltfm_host->clk)) {
|
||
|
|
ret = PTR_ERR(pltfm_host->clk);
|
||
|
|
goto err;
|
||
|
|
}
|
||
|
|
ret = clk_prepare_enable(pltfm_host->clk);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(dev, "failed to enable host clk\n");
|
||
|
|
goto err;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (iproc_host->data->missing_caps) {
|
||
|
|
__sdhci_read_caps(host, NULL,
|
||
|
|
&iproc_host->data->caps,
|
||
|
|
&iproc_host->data->caps1);
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = sdhci_add_host(host);
|
||
|
|
if (ret)
|
||
|
|
goto err_clk;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err_clk:
|
||
|
|
if (dev->of_node)
|
||
|
|
clk_disable_unprepare(pltfm_host->clk);
|
||
|
|
err:
|
||
|
|
sdhci_pltfm_free(pdev);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void sdhci_iproc_shutdown(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
sdhci_pltfm_suspend(&pdev->dev);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver sdhci_iproc_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "sdhci-iproc",
|
||
|
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
||
|
|
.of_match_table = sdhci_iproc_of_match,
|
||
|
|
.acpi_match_table = ACPI_PTR(sdhci_iproc_acpi_ids),
|
||
|
|
.pm = &sdhci_pltfm_pmops,
|
||
|
|
},
|
||
|
|
.probe = sdhci_iproc_probe,
|
||
|
|
.remove = sdhci_pltfm_unregister,
|
||
|
|
.shutdown = sdhci_iproc_shutdown,
|
||
|
|
};
|
||
|
|
module_platform_driver(sdhci_iproc_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Broadcom");
|
||
|
|
MODULE_DESCRIPTION("IPROC SDHCI driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|