2023-08-30 17:31:07 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* DWMAC4 DMA Header file.
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*
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* Copyright (C) 2007-2015 STMicroelectronics Ltd
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*
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* Author: Alexandre Torgue <alexandre.torgue@st.com>
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*/
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#ifndef __DWMAC4_DMA_H__
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#define __DWMAC4_DMA_H__
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/* Define the max channel number used for tx (also rx).
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* dwmac4 accepts up to 8 channels for TX (and also 8 channels for RX
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*/
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#define DMA_CHANNEL_NB_MAX 1
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#define DMA_BUS_MODE 0x00001000
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#define DMA_SYS_BUS_MODE 0x00001004
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#define DMA_STATUS 0x00001008
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#define DMA_DEBUG_STATUS_0 0x0000100c
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#define DMA_DEBUG_STATUS_1 0x00001010
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#define DMA_DEBUG_STATUS_2 0x00001014
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#define DMA_AXI_BUS_MODE 0x00001028
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#define DMA_TBS_CTRL 0x00001050
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/* DMA Bus Mode bitmap */
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#define DMA_BUS_MODE_DCHE BIT(19)
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#define DMA_BUS_MODE_INTM_MASK GENMASK(17, 16)
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#define DMA_BUS_MODE_INTM_SHIFT 16
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#define DMA_BUS_MODE_INTM_MODE1 0x1
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#define DMA_BUS_MODE_SFT_RESET BIT(0)
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/* DMA SYS Bus Mode bitmap */
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#define DMA_BUS_MODE_SPH BIT(24)
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#define DMA_BUS_MODE_PBL BIT(16)
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#define DMA_BUS_MODE_PBL_SHIFT 16
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#define DMA_BUS_MODE_RPBL_SHIFT 16
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#define DMA_BUS_MODE_MB BIT(14)
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#define DMA_BUS_MODE_FB BIT(0)
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/* DMA Interrupt top status */
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#define DMA_STATUS_MAC BIT(17)
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#define DMA_STATUS_MTL BIT(16)
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#define DMA_STATUS_CHAN7 BIT(7)
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#define DMA_STATUS_CHAN6 BIT(6)
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#define DMA_STATUS_CHAN5 BIT(5)
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#define DMA_STATUS_CHAN4 BIT(4)
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#define DMA_STATUS_CHAN3 BIT(3)
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#define DMA_STATUS_CHAN2 BIT(2)
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#define DMA_STATUS_CHAN1 BIT(1)
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#define DMA_STATUS_CHAN0 BIT(0)
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/* DMA debug status bitmap */
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#define DMA_DEBUG_STATUS_TS_MASK 0xf
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#define DMA_DEBUG_STATUS_RS_MASK 0xf
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/* DMA AXI bitmap */
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#define DMA_AXI_EN_LPI BIT(31)
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#define DMA_AXI_LPI_XIT_FRM BIT(30)
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#define DMA_AXI_WR_OSR_LMT GENMASK(27, 24)
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#define DMA_AXI_WR_OSR_LMT_SHIFT 24
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#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
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#define DMA_AXI_RD_OSR_LMT_SHIFT 16
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#define DMA_AXI_OSR_MAX 0xf
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#define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
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(DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
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#define DMA_SYS_BUS_MB BIT(14)
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#define DMA_AXI_1KBBE BIT(13)
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#define DMA_SYS_BUS_AAL BIT(12)
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#define DMA_SYS_BUS_EAME BIT(11)
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#define DMA_AXI_BLEN256 BIT(7)
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#define DMA_AXI_BLEN128 BIT(6)
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#define DMA_AXI_BLEN64 BIT(5)
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#define DMA_AXI_BLEN32 BIT(4)
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#define DMA_AXI_BLEN16 BIT(3)
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#define DMA_AXI_BLEN8 BIT(2)
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#define DMA_AXI_BLEN4 BIT(1)
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#define DMA_SYS_BUS_FB BIT(0)
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#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
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DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
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DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
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DMA_AXI_BLEN4)
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#define DMA_AXI_BURST_LEN_MASK 0x000000FE
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/* DMA TBS Control */
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#define DMA_TBS_FTOS GENMASK(31, 8)
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#define DMA_TBS_FTOV BIT(0)
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#define DMA_TBS_DEF_FTOS (DMA_TBS_FTOS | DMA_TBS_FTOV)
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/* Following DMA defines are chanels oriented */
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#define DMA_CHAN_BASE_ADDR 0x00001100
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#define DMA_CHAN_BASE_OFFSET 0x80
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2023-10-24 12:59:35 +02:00
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static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
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const u32 x)
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{
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u32 addr;
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if (addrs)
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addr = addrs->dma_chan + (x * addrs->dma_chan_offset);
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else
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addr = DMA_CHAN_BASE_ADDR + (x * DMA_CHAN_BASE_OFFSET);
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return addr;
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}
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2023-08-30 17:31:07 +02:00
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#define DMA_CHAN_REG_NUMBER 17
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2023-10-24 12:59:35 +02:00
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#define DMA_CHAN_CONTROL(addrs, x) dma_chanx_base_addr(addrs, x)
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#define DMA_CHAN_TX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4)
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#define DMA_CHAN_RX_CONTROL(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x8)
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#define DMA_CHAN_TX_BASE_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x10)
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#define DMA_CHAN_TX_BASE_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x14)
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#define DMA_CHAN_RX_BASE_ADDR_HI(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x18)
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#define DMA_CHAN_RX_BASE_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x1c)
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#define DMA_CHAN_TX_END_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x20)
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#define DMA_CHAN_RX_END_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x28)
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#define DMA_CHAN_TX_RING_LEN(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x2c)
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#define DMA_CHAN_RX_RING_LEN(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x30)
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#define DMA_CHAN_INTR_ENA(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x34)
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#define DMA_CHAN_RX_WATCHDOG(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x38)
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#define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x3c)
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#define DMA_CHAN_CUR_TX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x44)
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#define DMA_CHAN_CUR_RX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4c)
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#define DMA_CHAN_CUR_TX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x54)
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#define DMA_CHAN_CUR_RX_BUF_ADDR(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x5c)
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#define DMA_CHAN_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x60)
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2023-08-30 17:31:07 +02:00
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/* DMA Control X */
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#define DMA_CONTROL_SPH BIT(24)
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#define DMA_CONTROL_MSS_MASK GENMASK(13, 0)
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/* DMA Tx Channel X Control register defines */
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#define DMA_CONTROL_EDSE BIT(28)
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#define DMA_CONTROL_TSE BIT(12)
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#define DMA_CONTROL_OSP BIT(4)
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#define DMA_CONTROL_ST BIT(0)
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/* DMA Rx Channel X Control register defines */
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#define DMA_CONTROL_SR BIT(0)
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#define DMA_RBSZ_MASK GENMASK(14, 1)
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#define DMA_RBSZ_SHIFT 1
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/* Interrupt status per channel */
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#define DMA_CHAN_STATUS_REB GENMASK(21, 19)
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#define DMA_CHAN_STATUS_REB_SHIFT 19
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#define DMA_CHAN_STATUS_TEB GENMASK(18, 16)
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#define DMA_CHAN_STATUS_TEB_SHIFT 16
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#define DMA_CHAN_STATUS_NIS BIT(15)
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#define DMA_CHAN_STATUS_AIS BIT(14)
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#define DMA_CHAN_STATUS_CDE BIT(13)
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#define DMA_CHAN_STATUS_FBE BIT(12)
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#define DMA_CHAN_STATUS_ERI BIT(11)
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#define DMA_CHAN_STATUS_ETI BIT(10)
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#define DMA_CHAN_STATUS_RWT BIT(9)
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#define DMA_CHAN_STATUS_RPS BIT(8)
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#define DMA_CHAN_STATUS_RBU BIT(7)
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#define DMA_CHAN_STATUS_RI BIT(6)
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#define DMA_CHAN_STATUS_TBU BIT(2)
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#define DMA_CHAN_STATUS_TPS BIT(1)
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#define DMA_CHAN_STATUS_TI BIT(0)
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#define DMA_CHAN_STATUS_MSK_COMMON (DMA_CHAN_STATUS_NIS | \
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DMA_CHAN_STATUS_AIS | \
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DMA_CHAN_STATUS_CDE | \
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DMA_CHAN_STATUS_FBE)
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#define DMA_CHAN_STATUS_MSK_RX (DMA_CHAN_STATUS_REB | \
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DMA_CHAN_STATUS_ERI | \
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DMA_CHAN_STATUS_RWT | \
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DMA_CHAN_STATUS_RPS | \
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DMA_CHAN_STATUS_RBU | \
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DMA_CHAN_STATUS_RI | \
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DMA_CHAN_STATUS_MSK_COMMON)
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#define DMA_CHAN_STATUS_MSK_TX (DMA_CHAN_STATUS_ETI | \
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DMA_CHAN_STATUS_TBU | \
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DMA_CHAN_STATUS_TPS | \
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DMA_CHAN_STATUS_TI | \
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DMA_CHAN_STATUS_MSK_COMMON)
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/* Interrupt enable bits per channel */
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#define DMA_CHAN_INTR_ENA_NIE BIT(16)
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#define DMA_CHAN_INTR_ENA_AIE BIT(15)
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#define DMA_CHAN_INTR_ENA_NIE_4_10 BIT(15)
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#define DMA_CHAN_INTR_ENA_AIE_4_10 BIT(14)
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#define DMA_CHAN_INTR_ENA_CDE BIT(13)
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#define DMA_CHAN_INTR_ENA_FBE BIT(12)
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#define DMA_CHAN_INTR_ENA_ERE BIT(11)
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#define DMA_CHAN_INTR_ENA_ETE BIT(10)
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#define DMA_CHAN_INTR_ENA_RWE BIT(9)
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#define DMA_CHAN_INTR_ENA_RSE BIT(8)
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#define DMA_CHAN_INTR_ENA_RBUE BIT(7)
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#define DMA_CHAN_INTR_ENA_RIE BIT(6)
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#define DMA_CHAN_INTR_ENA_TBUE BIT(2)
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#define DMA_CHAN_INTR_ENA_TSE BIT(1)
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#define DMA_CHAN_INTR_ENA_TIE BIT(0)
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#define DMA_CHAN_INTR_NORMAL (DMA_CHAN_INTR_ENA_NIE | \
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DMA_CHAN_INTR_ENA_RIE | \
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DMA_CHAN_INTR_ENA_TIE)
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#define DMA_CHAN_INTR_ABNORMAL (DMA_CHAN_INTR_ENA_AIE | \
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DMA_CHAN_INTR_ENA_FBE)
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/* DMA default interrupt mask for 4.00 */
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#define DMA_CHAN_INTR_DEFAULT_MASK (DMA_CHAN_INTR_NORMAL | \
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DMA_CHAN_INTR_ABNORMAL)
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#define DMA_CHAN_INTR_DEFAULT_RX (DMA_CHAN_INTR_ENA_RIE)
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#define DMA_CHAN_INTR_DEFAULT_TX (DMA_CHAN_INTR_ENA_TIE)
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#define DMA_CHAN_INTR_NORMAL_4_10 (DMA_CHAN_INTR_ENA_NIE_4_10 | \
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DMA_CHAN_INTR_ENA_RIE | \
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DMA_CHAN_INTR_ENA_TIE)
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#define DMA_CHAN_INTR_ABNORMAL_4_10 (DMA_CHAN_INTR_ENA_AIE_4_10 | \
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DMA_CHAN_INTR_ENA_FBE)
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/* DMA default interrupt mask for 4.10a */
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#define DMA_CHAN_INTR_DEFAULT_MASK_4_10 (DMA_CHAN_INTR_NORMAL_4_10 | \
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DMA_CHAN_INTR_ABNORMAL_4_10)
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#define DMA_CHAN_INTR_DEFAULT_RX_4_10 (DMA_CHAN_INTR_ENA_RIE)
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#define DMA_CHAN_INTR_DEFAULT_TX_4_10 (DMA_CHAN_INTR_ENA_TIE)
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/* channel 0 specific fields */
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#define DMA_CHAN0_DBG_STAT_TPS GENMASK(15, 12)
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#define DMA_CHAN0_DBG_STAT_TPS_SHIFT 12
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#define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8)
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#define DMA_CHAN0_DBG_STAT_RPS_SHIFT 8
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int dwmac4_dma_reset(void __iomem *ioaddr);
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2023-10-24 12:59:35 +02:00
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void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
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u32 chan, bool rx, bool tx);
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void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
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u32 chan, bool rx, bool tx);
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void dwmac4_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
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u32 chan, bool rx, bool tx);
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void dwmac410_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
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u32 chan, bool rx, bool tx);
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void dwmac4_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
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u32 chan);
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void dwmac4_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
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u32 chan);
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void dwmac4_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
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u32 chan);
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void dwmac4_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
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u32 chan);
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int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
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2023-08-30 17:31:07 +02:00
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struct stmmac_extra_stats *x, u32 chan, u32 dir);
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2023-10-24 12:59:35 +02:00
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void dwmac4_set_rx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr,
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u32 len, u32 chan);
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void dwmac4_set_tx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr,
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u32 len, u32 chan);
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void dwmac4_set_rx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr,
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u32 tail_ptr, u32 chan);
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void dwmac4_set_tx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr,
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u32 tail_ptr, u32 chan);
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2023-08-30 17:31:07 +02:00
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#endif /* __DWMAC4_DMA_H__ */
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