259 lines
7.0 KiB
C
259 lines
7.0 KiB
C
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/*
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* Copyright (c) 2010-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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#include "hw-ops.h"
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#include "ar9003_phy.h"
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#include "ar9003_rtt.h"
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#define RTT_RESTORE_TIMEOUT 1000
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#define RTT_ACCESS_TIMEOUT 100
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#define RTT_BAD_VALUE 0x0bad0bad
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/*
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* RTT (Radio Retention Table) hardware implementation information
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*
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* There is an internal table (i.e. the rtt) for each chain (or bank).
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* Each table contains 6 entries and each entry is corresponding to
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* a specific calibration parameter as depicted below.
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* 0~2 - DC offset DAC calibration: loop, low, high (offsetI/Q_...)
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* 3 - Filter cal (filterfc)
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* 4 - RX gain settings
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* 5 - Peak detector offset calibration (agc_caldac)
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*/
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void ar9003_hw_rtt_enable(struct ath_hw *ah)
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{
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REG_WRITE(ah, AR_PHY_RTT_CTRL, 1);
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}
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void ar9003_hw_rtt_disable(struct ath_hw *ah)
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{
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REG_WRITE(ah, AR_PHY_RTT_CTRL, 0);
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}
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void ar9003_hw_rtt_set_mask(struct ath_hw *ah, u32 rtt_mask)
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{
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REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
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AR_PHY_RTT_CTRL_RESTORE_MASK, rtt_mask);
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}
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bool ar9003_hw_rtt_force_restore(struct ath_hw *ah)
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{
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if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
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AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
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0, RTT_RESTORE_TIMEOUT))
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return false;
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REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
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AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE, 1);
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if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
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AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
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0, RTT_RESTORE_TIMEOUT))
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return false;
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return true;
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}
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static void ar9003_hw_rtt_load_hist_entry(struct ath_hw *ah, u8 chain,
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u32 index, u32 data28)
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{
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u32 val;
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val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA);
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REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val);
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val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
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SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
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SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
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REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
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udelay(1);
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val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
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REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
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udelay(1);
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if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
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AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
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RTT_ACCESS_TIMEOUT))
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return;
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val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE);
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REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
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udelay(1);
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ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
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AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
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RTT_ACCESS_TIMEOUT);
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}
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void ar9003_hw_rtt_load_hist(struct ath_hw *ah)
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{
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int chain, i;
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for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
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if (!(ah->caps.rx_chainmask & (1 << chain)))
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continue;
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for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++) {
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ar9003_hw_rtt_load_hist_entry(ah, chain, i,
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ah->caldata->rtt_table[chain][i]);
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ath_dbg(ath9k_hw_common(ah), CALIBRATE,
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"Load RTT value at idx %d, chain %d: 0x%x\n",
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i, chain, ah->caldata->rtt_table[chain][i]);
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}
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}
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}
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static void ar9003_hw_patch_rtt(struct ath_hw *ah, int index, int chain)
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{
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int agc, caldac;
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if (!test_bit(SW_PKDET_DONE, &ah->caldata->cal_flags))
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return;
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if ((index != 5) || (chain >= 2))
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return;
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agc = REG_READ_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
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AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE);
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if (!agc)
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return;
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caldac = ah->caldata->caldac[chain];
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ah->caldata->rtt_table[chain][index] &= 0xFFFF05FF;
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caldac = (caldac & 0x20) | ((caldac & 0x1F) << 7);
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ah->caldata->rtt_table[chain][index] |= (caldac << 4);
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}
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static int ar9003_hw_rtt_fill_hist_entry(struct ath_hw *ah, u8 chain, u32 index)
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{
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u32 val;
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val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
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SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
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SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
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REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
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udelay(1);
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val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
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REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
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udelay(1);
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if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
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AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
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RTT_ACCESS_TIMEOUT))
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return RTT_BAD_VALUE;
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val = MS(REG_READ(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain)),
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AR_PHY_RTT_SW_RTT_TABLE_DATA);
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return val;
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}
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void ar9003_hw_rtt_fill_hist(struct ath_hw *ah)
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{
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int chain, i;
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for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
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if (!(ah->caps.rx_chainmask & (1 << chain)))
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continue;
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for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++) {
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ah->caldata->rtt_table[chain][i] =
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ar9003_hw_rtt_fill_hist_entry(ah, chain, i);
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ar9003_hw_patch_rtt(ah, i, chain);
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ath_dbg(ath9k_hw_common(ah), CALIBRATE,
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"RTT value at idx %d, chain %d is: 0x%x\n",
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i, chain, ah->caldata->rtt_table[chain][i]);
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}
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}
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set_bit(RTT_DONE, &ah->caldata->cal_flags);
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}
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void ar9003_hw_rtt_clear_hist(struct ath_hw *ah)
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{
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int chain, i;
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for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
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if (!(ah->caps.rx_chainmask & (1 << chain)))
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continue;
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for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++)
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ar9003_hw_rtt_load_hist_entry(ah, chain, i, 0);
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}
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if (ah->caldata)
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clear_bit(RTT_DONE, &ah->caldata->cal_flags);
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}
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bool ar9003_hw_rtt_restore(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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bool restore;
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if (!ah->caldata)
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return false;
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if (test_bit(SW_PKDET_DONE, &ah->caldata->cal_flags)) {
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if (IS_CHAN_2GHZ(chan)){
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REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(0),
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AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR,
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ah->caldata->caldac[0]);
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REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(1),
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AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR,
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ah->caldata->caldac[1]);
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} else {
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REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(0),
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AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR,
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ah->caldata->caldac[0]);
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REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(1),
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AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR,
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ah->caldata->caldac[1]);
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}
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REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(1),
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AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE, 0x1);
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REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(0),
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AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE, 0x1);
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}
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if (!test_bit(RTT_DONE, &ah->caldata->cal_flags))
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return false;
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ar9003_hw_rtt_enable(ah);
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if (test_bit(SW_PKDET_DONE, &ah->caldata->cal_flags))
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ar9003_hw_rtt_set_mask(ah, 0x30);
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else
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ar9003_hw_rtt_set_mask(ah, 0x10);
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if (!ath9k_hw_rfbus_req(ah)) {
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ath_err(ath9k_hw_common(ah), "Could not stop baseband\n");
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restore = false;
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goto fail;
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}
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ar9003_hw_rtt_load_hist(ah);
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restore = ar9003_hw_rtt_force_restore(ah);
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fail:
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ath9k_hw_rfbus_done(ah);
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ar9003_hw_rtt_disable(ah);
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return restore;
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}
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