319 lines
7.7 KiB
C
319 lines
7.7 KiB
C
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// SPDX-License-Identifier: ISC
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/*
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* Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "mt76x0.h"
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#include "mcu.h"
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static int mt76x0e_start(struct ieee80211_hw *hw)
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{
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struct mt76x02_dev *dev = hw->priv;
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mt76x02_mac_start(dev);
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mt76x0_phy_calibrate(dev, true);
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ieee80211_queue_delayed_work(dev->mt76.hw, &dev->mphy.mac_work,
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MT_MAC_WORK_INTERVAL);
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ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
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MT_CALIBRATE_INTERVAL);
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set_bit(MT76_STATE_RUNNING, &dev->mphy.state);
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return 0;
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}
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static void mt76x0e_stop_hw(struct mt76x02_dev *dev)
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{
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cancel_delayed_work_sync(&dev->cal_work);
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cancel_delayed_work_sync(&dev->mphy.mac_work);
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clear_bit(MT76_RESTART, &dev->mphy.state);
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if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY,
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0, 1000))
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dev_warn(dev->mt76.dev, "TX DMA did not stop\n");
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mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_EN);
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mt76x0_mac_stop(dev);
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if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
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0, 1000))
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dev_warn(dev->mt76.dev, "TX DMA did not stop\n");
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mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_RX_DMA_EN);
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}
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static void mt76x0e_stop(struct ieee80211_hw *hw)
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{
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struct mt76x02_dev *dev = hw->priv;
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clear_bit(MT76_STATE_RUNNING, &dev->mphy.state);
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mt76x0e_stop_hw(dev);
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}
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static void
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mt76x0e_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
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u32 queues, bool drop)
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{
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}
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static const struct ieee80211_ops mt76x0e_ops = {
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.tx = mt76x02_tx,
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.start = mt76x0e_start,
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.stop = mt76x0e_stop,
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.add_interface = mt76x02_add_interface,
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.remove_interface = mt76x02_remove_interface,
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.config = mt76x0_config,
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.configure_filter = mt76x02_configure_filter,
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.bss_info_changed = mt76x02_bss_info_changed,
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.sta_state = mt76_sta_state,
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.sta_pre_rcu_remove = mt76_sta_pre_rcu_remove,
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.set_key = mt76x02_set_key,
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.conf_tx = mt76x02_conf_tx,
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.sw_scan_start = mt76_sw_scan,
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.sw_scan_complete = mt76x02_sw_scan_complete,
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.ampdu_action = mt76x02_ampdu_action,
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.sta_rate_tbl_update = mt76x02_sta_rate_tbl_update,
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.wake_tx_queue = mt76_wake_tx_queue,
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.get_survey = mt76_get_survey,
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.get_txpower = mt76_get_txpower,
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.flush = mt76x0e_flush,
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.set_tim = mt76_set_tim,
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.release_buffered_frames = mt76_release_buffered_frames,
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.set_coverage_class = mt76x02_set_coverage_class,
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.set_rts_threshold = mt76x02_set_rts_threshold,
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.get_antenna = mt76_get_antenna,
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.reconfig_complete = mt76x02_reconfig_complete,
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.set_sar_specs = mt76x0_set_sar_specs,
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};
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static int mt76x0e_init_hardware(struct mt76x02_dev *dev, bool resume)
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{
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int err;
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mt76x0_chip_onoff(dev, true, false);
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if (!mt76x02_wait_for_mac(&dev->mt76))
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return -ETIMEDOUT;
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mt76x02_dma_disable(dev);
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err = mt76x0e_mcu_init(dev);
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if (err < 0)
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return err;
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if (!resume) {
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err = mt76x02_dma_init(dev);
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if (err < 0)
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return err;
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}
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err = mt76x0_init_hardware(dev);
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if (err < 0)
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return err;
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mt76x02e_init_beacon_config(dev);
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if (mt76_chip(&dev->mt76) == 0x7610) {
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u16 val;
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mt76_clear(dev, MT_COEXCFG0, BIT(0));
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val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0);
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if (!(val & MT_EE_NIC_CONF_0_PA_IO_CURRENT))
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mt76_set(dev, MT_XO_CTRL7, 0xc03);
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}
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mt76_clear(dev, 0x110, BIT(9));
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mt76_set(dev, MT_MAX_LEN_CFG, BIT(13));
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return 0;
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}
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static int mt76x0e_register_device(struct mt76x02_dev *dev)
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{
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int err;
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err = mt76x0e_init_hardware(dev, false);
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if (err < 0)
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return err;
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err = mt76x0_register_device(dev);
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if (err < 0)
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return err;
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set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
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return 0;
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}
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static int
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mt76x0e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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static const struct mt76_driver_ops drv_ops = {
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.txwi_size = sizeof(struct mt76x02_txwi),
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.drv_flags = MT_DRV_TX_ALIGNED4_SKBS |
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MT_DRV_SW_RX_AIRTIME,
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.survey_flags = SURVEY_INFO_TIME_TX,
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.update_survey = mt76x02_update_channel,
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.tx_prepare_skb = mt76x02_tx_prepare_skb,
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.tx_complete_skb = mt76x02_tx_complete_skb,
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.rx_skb = mt76x02_queue_rx_skb,
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.rx_poll_complete = mt76x02_rx_poll_complete,
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.sta_ps = mt76x02_sta_ps,
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.sta_add = mt76x02_sta_add,
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.sta_remove = mt76x02_sta_remove,
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};
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struct mt76x02_dev *dev;
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struct mt76_dev *mdev;
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int ret;
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ret = pcim_enable_device(pdev);
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if (ret)
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return ret;
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ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
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if (ret)
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return ret;
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pci_set_master(pdev);
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ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
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if (ret)
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return ret;
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mt76_pci_disable_aspm(pdev);
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mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt76x0e_ops,
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&drv_ops);
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if (!mdev)
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return -ENOMEM;
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dev = container_of(mdev, struct mt76x02_dev, mt76);
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mutex_init(&dev->phy_mutex);
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mt76_mmio_init(mdev, pcim_iomap_table(pdev)[0]);
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mdev->rev = mt76_rr(dev, MT_ASIC_VERSION);
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dev_info(mdev->dev, "ASIC revision: %08x\n", mdev->rev);
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mt76_wr(dev, MT_INT_MASK_CSR, 0);
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ret = devm_request_irq(mdev->dev, pdev->irq, mt76x02_irq_handler,
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IRQF_SHARED, KBUILD_MODNAME, dev);
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if (ret)
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goto error;
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ret = mt76x0e_register_device(dev);
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if (ret < 0)
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goto error;
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return 0;
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error:
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mt76_free_device(&dev->mt76);
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return ret;
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}
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static void mt76x0e_cleanup(struct mt76x02_dev *dev)
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{
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clear_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
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tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
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mt76x0_chip_onoff(dev, false, false);
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mt76x0e_stop_hw(dev);
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mt76_dma_cleanup(&dev->mt76);
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mt76x02_mcu_cleanup(dev);
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}
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static void
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mt76x0e_remove(struct pci_dev *pdev)
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{
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struct mt76_dev *mdev = pci_get_drvdata(pdev);
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struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
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mt76_unregister_device(mdev);
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mt76x0e_cleanup(dev);
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mt76_free_device(mdev);
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}
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#ifdef CONFIG_PM
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static int mt76x0e_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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struct mt76_dev *mdev = pci_get_drvdata(pdev);
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struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
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int i;
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mt76_worker_disable(&mdev->tx_worker);
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for (i = 0; i < ARRAY_SIZE(mdev->phy.q_tx); i++)
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mt76_queue_tx_cleanup(dev, mdev->phy.q_tx[i], true);
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for (i = 0; i < ARRAY_SIZE(mdev->q_mcu); i++)
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mt76_queue_tx_cleanup(dev, mdev->q_mcu[i], true);
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napi_disable(&mdev->tx_napi);
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mt76_for_each_q_rx(mdev, i)
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napi_disable(&mdev->napi[i]);
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mt76x02_dma_disable(dev);
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mt76x02_mcu_cleanup(dev);
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mt76x0_chip_onoff(dev, false, false);
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pci_enable_wake(pdev, pci_choose_state(pdev, state), true);
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pci_save_state(pdev);
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return pci_set_power_state(pdev, pci_choose_state(pdev, state));
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}
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static int mt76x0e_resume(struct pci_dev *pdev)
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{
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struct mt76_dev *mdev = pci_get_drvdata(pdev);
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struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
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int err, i;
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err = pci_set_power_state(pdev, PCI_D0);
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if (err)
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return err;
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pci_restore_state(pdev);
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mt76_worker_enable(&mdev->tx_worker);
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local_bh_disable();
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mt76_for_each_q_rx(mdev, i) {
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mt76_queue_rx_reset(dev, i);
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napi_enable(&mdev->napi[i]);
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napi_schedule(&mdev->napi[i]);
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}
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napi_enable(&mdev->tx_napi);
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napi_schedule(&mdev->tx_napi);
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local_bh_enable();
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return mt76x0e_init_hardware(dev, true);
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}
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#endif /* CONFIG_PM */
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static const struct pci_device_id mt76x0e_device_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7610) },
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{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7630) },
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{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7650) },
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{ },
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};
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MODULE_DEVICE_TABLE(pci, mt76x0e_device_table);
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MODULE_FIRMWARE(MT7610E_FIRMWARE);
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MODULE_FIRMWARE(MT7650E_FIRMWARE);
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MODULE_LICENSE("Dual BSD/GPL");
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static struct pci_driver mt76x0e_driver = {
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.name = KBUILD_MODNAME,
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.id_table = mt76x0e_device_table,
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.probe = mt76x0e_probe,
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.remove = mt76x0e_remove,
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#ifdef CONFIG_PM
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.suspend = mt76x0e_suspend,
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.resume = mt76x0e_resume,
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#endif /* CONFIG_PM */
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};
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module_pci_driver(mt76x0e_driver);
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