385 lines
8.5 KiB
C
385 lines
8.5 KiB
C
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// SPDX-License-Identifier: ISC
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/* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Felix Fietkau <nbd@nbd.name>
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* Lorenzo Bianconi <lorenzo@kernel.org>
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* Sean Wang <sean.wang@mediatek.com>
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*/
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#include <linux/kernel.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sdio_ids.h>
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#include <linux/mmc/sdio_func.h>
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#include "trace.h"
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#include "sdio.h"
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#include "mt76.h"
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static int mt76s_refill_sched_quota(struct mt76_dev *dev, u32 *data)
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{
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u32 ple_ac_data_quota[] = {
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FIELD_GET(TXQ_CNT_L, data[4]), /* VO */
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FIELD_GET(TXQ_CNT_H, data[3]), /* VI */
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FIELD_GET(TXQ_CNT_L, data[3]), /* BE */
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FIELD_GET(TXQ_CNT_H, data[2]), /* BK */
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};
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u32 pse_ac_data_quota[] = {
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FIELD_GET(TXQ_CNT_H, data[1]), /* VO */
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FIELD_GET(TXQ_CNT_L, data[1]), /* VI */
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FIELD_GET(TXQ_CNT_H, data[0]), /* BE */
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FIELD_GET(TXQ_CNT_L, data[0]), /* BK */
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};
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u32 pse_mcu_quota = FIELD_GET(TXQ_CNT_L, data[2]);
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u32 pse_data_quota = 0, ple_data_quota = 0;
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struct mt76_sdio *sdio = &dev->sdio;
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int i;
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for (i = 0; i < ARRAY_SIZE(pse_ac_data_quota); i++) {
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pse_data_quota += pse_ac_data_quota[i];
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ple_data_quota += ple_ac_data_quota[i];
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}
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if (!pse_data_quota && !ple_data_quota && !pse_mcu_quota)
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return 0;
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sdio->sched.pse_mcu_quota += pse_mcu_quota;
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sdio->sched.pse_data_quota += pse_data_quota;
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sdio->sched.ple_data_quota += ple_data_quota;
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return pse_data_quota + ple_data_quota + pse_mcu_quota;
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}
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static struct sk_buff *
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mt76s_build_rx_skb(void *data, int data_len, int buf_len)
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{
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int len = min_t(int, data_len, MT_SKB_HEAD_LEN);
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struct sk_buff *skb;
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skb = alloc_skb(len, GFP_KERNEL);
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if (!skb)
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return NULL;
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skb_put_data(skb, data, len);
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if (data_len > len) {
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struct page *page;
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data += len;
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page = virt_to_head_page(data);
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skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
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page, data - page_address(page),
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data_len - len, buf_len);
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get_page(page);
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}
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return skb;
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}
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static int
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mt76s_rx_run_queue(struct mt76_dev *dev, enum mt76_rxq_id qid,
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struct mt76s_intr *intr)
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{
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struct mt76_queue *q = &dev->q_rx[qid];
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struct mt76_sdio *sdio = &dev->sdio;
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int len = 0, err, i;
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struct page *page;
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u8 *buf, *end;
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for (i = 0; i < intr->rx.num[qid]; i++)
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len += round_up(intr->rx.len[qid][i] + 4, 4);
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if (!len)
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return 0;
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if (len > sdio->func->cur_blksize)
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len = roundup(len, sdio->func->cur_blksize);
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page = __dev_alloc_pages(GFP_KERNEL, get_order(len));
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if (!page)
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return -ENOMEM;
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buf = page_address(page);
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sdio_claim_host(sdio->func);
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err = sdio_readsb(sdio->func, buf, MCR_WRDR(qid), len);
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sdio_release_host(sdio->func);
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if (err < 0) {
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dev_err(dev->dev, "sdio read data failed:%d\n", err);
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put_page(page);
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return err;
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}
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end = buf + len;
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i = 0;
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while (i < intr->rx.num[qid] && buf < end) {
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int index = (q->head + i) % q->ndesc;
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struct mt76_queue_entry *e = &q->entry[index];
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__le32 *rxd = (__le32 *)buf;
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/* parse rxd to get the actual packet length */
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len = le32_get_bits(rxd[0], GENMASK(15, 0));
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/* Optimized path for TXS */
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if (!dev->drv->rx_check || dev->drv->rx_check(dev, buf, len)) {
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e->skb = mt76s_build_rx_skb(buf, len,
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round_up(len + 4, 4));
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if (!e->skb)
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break;
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if (q->queued + i + 1 == q->ndesc)
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break;
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i++;
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}
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buf += round_up(len + 4, 4);
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}
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put_page(page);
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spin_lock_bh(&q->lock);
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q->head = (q->head + i) % q->ndesc;
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q->queued += i;
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spin_unlock_bh(&q->lock);
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return i;
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}
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static int mt76s_rx_handler(struct mt76_dev *dev)
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{
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struct mt76_sdio *sdio = &dev->sdio;
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struct mt76s_intr intr;
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int nframes = 0, ret;
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ret = sdio->parse_irq(dev, &intr);
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if (ret)
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return ret;
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trace_dev_irq(dev, intr.isr, 0);
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if (intr.isr & WHIER_RX0_DONE_INT_EN) {
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ret = mt76s_rx_run_queue(dev, 0, &intr);
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if (ret > 0) {
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mt76_worker_schedule(&sdio->net_worker);
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nframes += ret;
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}
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}
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if (intr.isr & WHIER_RX1_DONE_INT_EN) {
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ret = mt76s_rx_run_queue(dev, 1, &intr);
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if (ret > 0) {
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mt76_worker_schedule(&sdio->net_worker);
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nframes += ret;
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}
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}
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nframes += !!mt76s_refill_sched_quota(dev, intr.tx.wtqcr);
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return nframes;
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}
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static int
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mt76s_tx_pick_quota(struct mt76_sdio *sdio, bool mcu, int buf_sz,
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int *pse_size, int *ple_size)
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{
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int pse_sz;
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pse_sz = DIV_ROUND_UP(buf_sz + sdio->sched.deficit,
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sdio->sched.pse_page_size);
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if (mcu && sdio->hw_ver == MT76_CONNAC2_SDIO)
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pse_sz = 1;
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if (mcu) {
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if (sdio->sched.pse_mcu_quota < *pse_size + pse_sz)
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return -EBUSY;
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} else {
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if (sdio->sched.pse_data_quota < *pse_size + pse_sz ||
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sdio->sched.ple_data_quota < *ple_size + 1)
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return -EBUSY;
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*ple_size = *ple_size + 1;
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}
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*pse_size = *pse_size + pse_sz;
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return 0;
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}
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static void
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mt76s_tx_update_quota(struct mt76_sdio *sdio, bool mcu, int pse_size,
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int ple_size)
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{
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if (mcu) {
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sdio->sched.pse_mcu_quota -= pse_size;
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} else {
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sdio->sched.pse_data_quota -= pse_size;
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sdio->sched.ple_data_quota -= ple_size;
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}
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}
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static int __mt76s_xmit_queue(struct mt76_dev *dev, u8 *data, int len)
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{
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struct mt76_sdio *sdio = &dev->sdio;
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int err;
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if (len > sdio->func->cur_blksize)
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len = roundup(len, sdio->func->cur_blksize);
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sdio_claim_host(sdio->func);
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err = sdio_writesb(sdio->func, MCR_WTDR1, data, len);
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sdio_release_host(sdio->func);
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if (err)
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dev_err(dev->dev, "sdio write failed: %d\n", err);
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return err;
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}
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static int mt76s_tx_run_queue(struct mt76_dev *dev, struct mt76_queue *q)
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{
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int err, nframes = 0, len = 0, pse_sz = 0, ple_sz = 0;
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bool mcu = q == dev->q_mcu[MT_MCUQ_WM];
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struct mt76_sdio *sdio = &dev->sdio;
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u8 pad;
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while (q->first != q->head) {
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struct mt76_queue_entry *e = &q->entry[q->first];
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struct sk_buff *iter;
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smp_rmb();
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if (test_bit(MT76_MCU_RESET, &dev->phy.state))
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goto next;
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if (!test_bit(MT76_STATE_MCU_RUNNING, &dev->phy.state)) {
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__skb_put_zero(e->skb, 4);
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err = __skb_grow(e->skb, roundup(e->skb->len,
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sdio->func->cur_blksize));
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if (err)
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return err;
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err = __mt76s_xmit_queue(dev, e->skb->data,
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e->skb->len);
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if (err)
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return err;
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goto next;
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}
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pad = roundup(e->skb->len, 4) - e->skb->len;
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if (len + e->skb->len + pad + 4 > dev->sdio.xmit_buf_sz)
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break;
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if (mt76s_tx_pick_quota(sdio, mcu, e->buf_sz, &pse_sz,
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&ple_sz))
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break;
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memcpy(sdio->xmit_buf + len, e->skb->data, skb_headlen(e->skb));
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len += skb_headlen(e->skb);
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nframes++;
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skb_walk_frags(e->skb, iter) {
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memcpy(sdio->xmit_buf + len, iter->data, iter->len);
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len += iter->len;
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nframes++;
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}
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if (unlikely(pad)) {
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memset(sdio->xmit_buf + len, 0, pad);
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len += pad;
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}
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next:
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q->first = (q->first + 1) % q->ndesc;
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e->done = true;
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}
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if (nframes) {
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memset(sdio->xmit_buf + len, 0, 4);
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err = __mt76s_xmit_queue(dev, sdio->xmit_buf, len + 4);
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if (err)
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return err;
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}
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mt76s_tx_update_quota(sdio, mcu, pse_sz, ple_sz);
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mt76_worker_schedule(&sdio->status_worker);
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return nframes;
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}
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void mt76s_txrx_worker(struct mt76_sdio *sdio)
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{
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struct mt76_dev *dev = container_of(sdio, struct mt76_dev, sdio);
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int i, nframes, ret;
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/* disable interrupt */
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sdio_claim_host(sdio->func);
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sdio_writel(sdio->func, WHLPCR_INT_EN_CLR, MCR_WHLPCR, NULL);
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sdio_release_host(sdio->func);
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do {
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nframes = 0;
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/* tx */
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for (i = 0; i <= MT_TXQ_PSD; i++) {
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ret = mt76s_tx_run_queue(dev, dev->phy.q_tx[i]);
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if (ret > 0)
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nframes += ret;
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}
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ret = mt76s_tx_run_queue(dev, dev->q_mcu[MT_MCUQ_WM]);
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if (ret > 0)
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nframes += ret;
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/* rx */
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ret = mt76s_rx_handler(dev);
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if (ret > 0)
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nframes += ret;
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if (test_bit(MT76_MCU_RESET, &dev->phy.state) ||
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test_bit(MT76_STATE_SUSPEND, &dev->phy.state)) {
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if (!mt76s_txqs_empty(dev))
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continue;
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else
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wake_up(&sdio->wait);
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}
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} while (nframes > 0);
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/* enable interrupt */
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sdio_claim_host(sdio->func);
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sdio_writel(sdio->func, WHLPCR_INT_EN_SET, MCR_WHLPCR, NULL);
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sdio_release_host(sdio->func);
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}
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EXPORT_SYMBOL_GPL(mt76s_txrx_worker);
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void mt76s_sdio_irq(struct sdio_func *func)
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{
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struct mt76_dev *dev = sdio_get_drvdata(func);
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struct mt76_sdio *sdio = &dev->sdio;
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if (!test_bit(MT76_STATE_INITIALIZED, &dev->phy.state) ||
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test_bit(MT76_MCU_RESET, &dev->phy.state))
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return;
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sdio_writel(sdio->func, WHLPCR_INT_EN_CLR, MCR_WHLPCR, NULL);
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mt76_worker_schedule(&sdio->txrx_worker);
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}
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EXPORT_SYMBOL_GPL(mt76s_sdio_irq);
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bool mt76s_txqs_empty(struct mt76_dev *dev)
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{
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struct mt76_queue *q;
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int i;
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for (i = 0; i <= MT_TXQ_PSD + 1; i++) {
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if (i <= MT_TXQ_PSD)
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q = dev->phy.q_tx[i];
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else
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q = dev->q_mcu[MT_MCUQ_WM];
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if (q->first != q->head)
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return false;
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}
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return true;
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}
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EXPORT_SYMBOL_GPL(mt76s_txqs_empty);
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