179 lines
5.9 KiB
C
179 lines
5.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright (C) 2021 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@gmail.com>
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*/
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#ifndef __REG_SDIO_H_
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#define __REG_SDIO_H_
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/* I/O bus domain address mapping */
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#define SDIO_LOCAL_OFFSET 0x10250000
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#define WLAN_IOREG_OFFSET 0x10260000
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#define FIRMWARE_FIFO_OFFSET 0x10270000
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#define TX_HIQ_OFFSET 0x10310000
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#define TX_MIQ_OFFSET 0x10320000
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#define TX_LOQ_OFFSET 0x10330000
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#define TX_EPQ_OFFSET 0x10350000
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#define RX_RX0FF_OFFSET 0x10340000
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#define RTW_SDIO_BUS_MSK 0xffff0000
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#define SDIO_LOCAL_REG_MSK 0x00000fff
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#define WLAN_IOREG_REG_MSK 0x0000ffff
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/* SDIO Tx Control */
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#define REG_SDIO_TX_CTRL (SDIO_LOCAL_OFFSET + 0x0000)
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/*SDIO status timeout*/
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#define REG_SDIO_TIMEOUT (SDIO_LOCAL_OFFSET + 0x0002)
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/* SDIO Host Interrupt Mask */
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#define REG_SDIO_HIMR (SDIO_LOCAL_OFFSET + 0x0014)
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#define REG_SDIO_HIMR_RX_REQUEST BIT(0)
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#define REG_SDIO_HIMR_AVAL BIT(1)
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#define REG_SDIO_HIMR_TXERR BIT(2)
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#define REG_SDIO_HIMR_RXERR BIT(3)
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#define REG_SDIO_HIMR_TXFOVW BIT(4)
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#define REG_SDIO_HIMR_RXFOVW BIT(5)
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#define REG_SDIO_HIMR_TXBCNOK BIT(6)
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#define REG_SDIO_HIMR_TXBCNERR BIT(7)
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#define REG_SDIO_HIMR_BCNERLY_INT BIT(16)
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#define REG_SDIO_HIMR_C2HCMD BIT(17)
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#define REG_SDIO_HIMR_CPWM1 BIT(18)
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#define REG_SDIO_HIMR_CPWM2 BIT(19)
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#define REG_SDIO_HIMR_HSISR_IND BIT(20)
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#define REG_SDIO_HIMR_GTINT3_IND BIT(21)
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#define REG_SDIO_HIMR_GTINT4_IND BIT(22)
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#define REG_SDIO_HIMR_PSTIMEOUT BIT(23)
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#define REG_SDIO_HIMR_OCPINT BIT(24)
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#define REG_SDIO_HIMR_ATIMEND BIT(25)
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#define REG_SDIO_HIMR_ATIMEND_E BIT(26)
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#define REG_SDIO_HIMR_CTWEND BIT(27)
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/* the following two are RTL8188 SDIO Specific */
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#define REG_SDIO_HIMR_MCU_ERR BIT(28)
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#define REG_SDIO_HIMR_TSF_BIT32_TOGGLE BIT(29)
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/* SDIO Host Interrupt Service Routine */
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#define REG_SDIO_HISR (SDIO_LOCAL_OFFSET + 0x0018)
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#define REG_SDIO_HISR_RX_REQUEST BIT(0)
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#define REG_SDIO_HISR_AVAL BIT(1)
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#define REG_SDIO_HISR_TXERR BIT(2)
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#define REG_SDIO_HISR_RXERR BIT(3)
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#define REG_SDIO_HISR_TXFOVW BIT(4)
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#define REG_SDIO_HISR_RXFOVW BIT(5)
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#define REG_SDIO_HISR_TXBCNOK BIT(6)
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#define REG_SDIO_HISR_TXBCNERR BIT(7)
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#define REG_SDIO_HISR_BCNERLY_INT BIT(16)
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#define REG_SDIO_HISR_C2HCMD BIT(17)
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#define REG_SDIO_HISR_CPWM1 BIT(18)
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#define REG_SDIO_HISR_CPWM2 BIT(19)
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#define REG_SDIO_HISR_HSISR_IND BIT(20)
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#define REG_SDIO_HISR_GTINT3_IND BIT(21)
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#define REG_SDIO_HISR_GTINT4_IND BIT(22)
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#define REG_SDIO_HISR_PSTIMEOUT BIT(23)
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#define REG_SDIO_HISR_OCPINT BIT(24)
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#define REG_SDIO_HISR_ATIMEND BIT(25)
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#define REG_SDIO_HISR_ATIMEND_E BIT(26)
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#define REG_SDIO_HISR_CTWEND BIT(27)
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/* the following two are RTL8188 SDIO Specific */
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#define REG_SDIO_HISR_MCU_ERR BIT(28)
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#define REG_SDIO_HISR_TSF_BIT32_TOGGLE BIT(29)
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/* HCI Current Power Mode */
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#define REG_SDIO_HCPWM (SDIO_LOCAL_OFFSET + 0x0019)
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/* RXDMA Request Length */
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#define REG_SDIO_RX0_REQ_LEN (SDIO_LOCAL_OFFSET + 0x001C)
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/* OQT Free Page */
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#define REG_SDIO_OQT_FREE_PG (SDIO_LOCAL_OFFSET + 0x001E)
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/* Free Tx Buffer Page */
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#define REG_SDIO_FREE_TXPG (SDIO_LOCAL_OFFSET + 0x0020)
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/* HCI Current Power Mode 1 */
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#define REG_SDIO_HCPWM1 (SDIO_LOCAL_OFFSET + 0x0024)
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/* HCI Current Power Mode 2 */
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#define REG_SDIO_HCPWM2 (SDIO_LOCAL_OFFSET + 0x0026)
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/* Free Tx Page Sequence */
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#define REG_SDIO_FREE_TXPG_SEQ (SDIO_LOCAL_OFFSET + 0x0028)
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/* HTSF Information */
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#define REG_SDIO_HTSFR_INFO (SDIO_LOCAL_OFFSET + 0x0030)
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#define REG_SDIO_HCPWM1_V2 (SDIO_LOCAL_OFFSET + 0x0038)
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/* H2C */
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#define REG_SDIO_H2C (SDIO_LOCAL_OFFSET + 0x0060)
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/* HCI Request Power Mode 1 */
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#define REG_SDIO_HRPWM1 (SDIO_LOCAL_OFFSET + 0x0080)
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/* HCI Request Power Mode 2 */
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#define REG_SDIO_HRPWM2 (SDIO_LOCAL_OFFSET + 0x0082)
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/* HCI Power Save Clock */
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#define REG_SDIO_HPS_CLKR (SDIO_LOCAL_OFFSET + 0x0084)
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/* SDIO HCI Suspend Control */
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#define REG_SDIO_HSUS_CTRL (SDIO_LOCAL_OFFSET + 0x0086)
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#define BIT_HCI_SUS_REQ BIT(0)
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#define BIT_HCI_RESUME_RDY BIT(1)
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/* SDIO Host Extension Interrupt Mask Always */
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#define REG_SDIO_HIMR_ON (SDIO_LOCAL_OFFSET + 0x0090)
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/* SDIO Host Extension Interrupt Status Always */
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#define REG_SDIO_HISR_ON (SDIO_LOCAL_OFFSET + 0x0091)
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#define REG_SDIO_INDIRECT_REG_CFG (SDIO_LOCAL_OFFSET + 0x0040)
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#define BIT_SDIO_INDIRECT_REG_CFG_WORD BIT(16)
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#define BIT_SDIO_INDIRECT_REG_CFG_DWORD BIT(17)
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#define BIT_SDIO_INDIRECT_REG_CFG_WRITE BIT(18)
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#define BIT_SDIO_INDIRECT_REG_CFG_READ BIT(19)
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#define BIT_SDIO_INDIRECT_REG_CFG_UNK20 BIT(20)
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#define REG_SDIO_INDIRECT_REG_DATA (SDIO_LOCAL_OFFSET + 0x0044)
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/* Sdio Address for SDIO Local Reg, TRX FIFO, MAC Reg */
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#define REG_SDIO_CMD_ADDR_MSK GENMASK(16, 13)
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#define REG_SDIO_CMD_ADDR_SDIO_REG 0
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#define REG_SDIO_CMD_ADDR_MAC_REG 8
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#define REG_SDIO_CMD_ADDR_TXFF_HIGH 4
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#define REG_SDIO_CMD_ADDR_TXFF_LOW 6
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#define REG_SDIO_CMD_ADDR_TXFF_NORMAL 5
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#define REG_SDIO_CMD_ADDR_TXFF_EXTRA 7
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#define REG_SDIO_CMD_ADDR_RXFF 7
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#define RTW_SDIO_BLOCK_SIZE 512
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#define RTW_SDIO_ADDR_RX_RX0FF_GEN(_id) (0x0e000 | ((_id) & 0x3))
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#define RTW_SDIO_DATA_PTR_ALIGN 8
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struct sdio_func;
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struct sdio_device_id;
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struct rtw_sdio_tx_data {
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u8 sn;
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};
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struct rtw_sdio_work_data {
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struct work_struct work;
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struct rtw_dev *rtwdev;
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};
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struct rtw_sdio {
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struct sdio_func *sdio_func;
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u32 irq_mask;
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u8 rx_addr;
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bool sdio3_bus_mode;
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void *irq_thread;
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struct workqueue_struct *txwq;
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struct rtw_sdio_work_data *tx_handler_data;
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struct sk_buff_head tx_queue[RTK_MAX_TX_QUEUE_NUM];
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};
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extern const struct dev_pm_ops rtw_sdio_pm_ops;
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int rtw_sdio_probe(struct sdio_func *sdio_func,
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const struct sdio_device_id *id);
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void rtw_sdio_remove(struct sdio_func *sdio_func);
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void rtw_sdio_shutdown(struct device *dev);
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static inline bool rtw_sdio_is_sdio30_supported(struct rtw_dev *rtwdev)
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{
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struct rtw_sdio *rtwsdio = (struct rtw_sdio *)rtwdev->priv;
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return rtwsdio->sdio3_bus_mode;
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}
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#endif
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