459 lines
12 KiB
C
459 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCI EPF driver for MHI Endpoint devices
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*
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* Copyright (C) 2023 Linaro Ltd.
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <linux/mhi_ep.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pci-epc.h>
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#include <linux/pci-epf.h>
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#define MHI_VERSION_1_0 0x01000000
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#define to_epf_mhi(cntrl) container_of(cntrl, struct pci_epf_mhi, cntrl)
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struct pci_epf_mhi_ep_info {
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const struct mhi_ep_cntrl_config *config;
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struct pci_epf_header *epf_header;
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enum pci_barno bar_num;
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u32 epf_flags;
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u32 msi_count;
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u32 mru;
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};
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#define MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, direction) \
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{ \
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.num = ch_num, \
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.name = ch_name, \
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.dir = direction, \
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}
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#define MHI_EP_CHANNEL_CONFIG_UL(ch_num, ch_name) \
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MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, DMA_TO_DEVICE)
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#define MHI_EP_CHANNEL_CONFIG_DL(ch_num, ch_name) \
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MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, DMA_FROM_DEVICE)
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static const struct mhi_ep_channel_config mhi_v1_channels[] = {
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MHI_EP_CHANNEL_CONFIG_UL(0, "LOOPBACK"),
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MHI_EP_CHANNEL_CONFIG_DL(1, "LOOPBACK"),
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MHI_EP_CHANNEL_CONFIG_UL(2, "SAHARA"),
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MHI_EP_CHANNEL_CONFIG_DL(3, "SAHARA"),
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MHI_EP_CHANNEL_CONFIG_UL(4, "DIAG"),
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MHI_EP_CHANNEL_CONFIG_DL(5, "DIAG"),
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MHI_EP_CHANNEL_CONFIG_UL(6, "SSR"),
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MHI_EP_CHANNEL_CONFIG_DL(7, "SSR"),
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MHI_EP_CHANNEL_CONFIG_UL(8, "QDSS"),
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MHI_EP_CHANNEL_CONFIG_DL(9, "QDSS"),
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MHI_EP_CHANNEL_CONFIG_UL(10, "EFS"),
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MHI_EP_CHANNEL_CONFIG_DL(11, "EFS"),
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MHI_EP_CHANNEL_CONFIG_UL(12, "MBIM"),
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MHI_EP_CHANNEL_CONFIG_DL(13, "MBIM"),
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MHI_EP_CHANNEL_CONFIG_UL(14, "QMI"),
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MHI_EP_CHANNEL_CONFIG_DL(15, "QMI"),
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MHI_EP_CHANNEL_CONFIG_UL(16, "QMI"),
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MHI_EP_CHANNEL_CONFIG_DL(17, "QMI"),
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MHI_EP_CHANNEL_CONFIG_UL(18, "IP-CTRL-1"),
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MHI_EP_CHANNEL_CONFIG_DL(19, "IP-CTRL-1"),
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MHI_EP_CHANNEL_CONFIG_UL(20, "IPCR"),
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MHI_EP_CHANNEL_CONFIG_DL(21, "IPCR"),
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MHI_EP_CHANNEL_CONFIG_UL(32, "DUN"),
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MHI_EP_CHANNEL_CONFIG_DL(33, "DUN"),
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MHI_EP_CHANNEL_CONFIG_UL(46, "IP_SW0"),
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MHI_EP_CHANNEL_CONFIG_DL(47, "IP_SW0"),
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};
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static const struct mhi_ep_cntrl_config mhi_v1_config = {
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.max_channels = 128,
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.num_channels = ARRAY_SIZE(mhi_v1_channels),
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.ch_cfg = mhi_v1_channels,
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.mhi_version = MHI_VERSION_1_0,
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};
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static struct pci_epf_header sdx55_header = {
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.vendorid = PCI_VENDOR_ID_QCOM,
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.deviceid = 0x0306,
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.baseclass_code = PCI_BASE_CLASS_COMMUNICATION,
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.subclass_code = PCI_CLASS_COMMUNICATION_MODEM & 0xff,
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.interrupt_pin = PCI_INTERRUPT_INTA,
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};
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static const struct pci_epf_mhi_ep_info sdx55_info = {
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.config = &mhi_v1_config,
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.epf_header = &sdx55_header,
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.bar_num = BAR_0,
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.epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32,
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.msi_count = 32,
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.mru = 0x8000,
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};
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struct pci_epf_mhi {
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const struct pci_epf_mhi_ep_info *info;
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struct mhi_ep_cntrl mhi_cntrl;
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struct pci_epf *epf;
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struct mutex lock;
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void __iomem *mmio;
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resource_size_t mmio_phys;
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u32 mmio_size;
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int irq;
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};
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static int __pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr,
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phys_addr_t *paddr, void __iomem **vaddr,
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size_t offset, size_t size)
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{
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struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
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struct pci_epf *epf = epf_mhi->epf;
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struct pci_epc *epc = epf->epc;
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int ret;
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*vaddr = pci_epc_mem_alloc_addr(epc, paddr, size + offset);
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if (!*vaddr)
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return -ENOMEM;
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ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, *paddr,
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pci_addr - offset, size + offset);
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if (ret) {
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pci_epc_mem_free_addr(epc, *paddr, *vaddr, size + offset);
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return ret;
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}
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*paddr = *paddr + offset;
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*vaddr = *vaddr + offset;
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return 0;
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}
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static int pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr,
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phys_addr_t *paddr, void __iomem **vaddr,
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size_t size)
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{
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struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
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struct pci_epc *epc = epf_mhi->epf->epc;
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size_t offset = pci_addr & (epc->mem->window.page_size - 1);
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return __pci_epf_mhi_alloc_map(mhi_cntrl, pci_addr, paddr, vaddr,
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offset, size);
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}
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static void __pci_epf_mhi_unmap_free(struct mhi_ep_cntrl *mhi_cntrl,
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u64 pci_addr, phys_addr_t paddr,
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void __iomem *vaddr, size_t offset,
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size_t size)
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{
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struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
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struct pci_epf *epf = epf_mhi->epf;
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struct pci_epc *epc = epf->epc;
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pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, paddr - offset);
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pci_epc_mem_free_addr(epc, paddr - offset, vaddr - offset,
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size + offset);
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}
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static void pci_epf_mhi_unmap_free(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr,
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phys_addr_t paddr, void __iomem *vaddr,
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size_t size)
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{
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struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
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struct pci_epf *epf = epf_mhi->epf;
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struct pci_epc *epc = epf->epc;
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size_t offset = pci_addr & (epc->mem->window.page_size - 1);
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__pci_epf_mhi_unmap_free(mhi_cntrl, pci_addr, paddr, vaddr, offset,
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size);
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}
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static void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl, u32 vector)
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{
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struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
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struct pci_epf *epf = epf_mhi->epf;
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struct pci_epc *epc = epf->epc;
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/*
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* MHI supplies 0 based MSI vectors but the API expects the vector
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* number to start from 1, so we need to increment the vector by 1.
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*/
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pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_EPC_IRQ_MSI,
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vector + 1);
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}
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static int pci_epf_mhi_read_from_host(struct mhi_ep_cntrl *mhi_cntrl, u64 from,
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void *to, size_t size)
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{
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struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
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size_t offset = from % SZ_4K;
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void __iomem *tre_buf;
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phys_addr_t tre_phys;
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int ret;
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mutex_lock(&epf_mhi->lock);
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ret = __pci_epf_mhi_alloc_map(mhi_cntrl, from, &tre_phys, &tre_buf,
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offset, size);
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if (ret) {
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mutex_unlock(&epf_mhi->lock);
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return ret;
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}
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memcpy_fromio(to, tre_buf, size);
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__pci_epf_mhi_unmap_free(mhi_cntrl, from, tre_phys, tre_buf, offset,
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size);
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mutex_unlock(&epf_mhi->lock);
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return 0;
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}
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static int pci_epf_mhi_write_to_host(struct mhi_ep_cntrl *mhi_cntrl,
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void *from, u64 to, size_t size)
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{
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struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl);
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size_t offset = to % SZ_4K;
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void __iomem *tre_buf;
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phys_addr_t tre_phys;
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int ret;
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mutex_lock(&epf_mhi->lock);
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ret = __pci_epf_mhi_alloc_map(mhi_cntrl, to, &tre_phys, &tre_buf,
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offset, size);
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if (ret) {
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mutex_unlock(&epf_mhi->lock);
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return ret;
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}
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memcpy_toio(tre_buf, from, size);
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__pci_epf_mhi_unmap_free(mhi_cntrl, to, tre_phys, tre_buf, offset,
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size);
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mutex_unlock(&epf_mhi->lock);
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return 0;
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}
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static int pci_epf_mhi_core_init(struct pci_epf *epf)
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{
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struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf);
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const struct pci_epf_mhi_ep_info *info = epf_mhi->info;
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struct pci_epf_bar *epf_bar = &epf->bar[info->bar_num];
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struct pci_epc *epc = epf->epc;
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struct device *dev = &epf->dev;
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int ret;
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epf_bar->phys_addr = epf_mhi->mmio_phys;
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epf_bar->size = epf_mhi->mmio_size;
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epf_bar->barno = info->bar_num;
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epf_bar->flags = info->epf_flags;
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ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar);
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if (ret) {
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dev_err(dev, "Failed to set BAR: %d\n", ret);
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return ret;
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}
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ret = pci_epc_set_msi(epc, epf->func_no, epf->vfunc_no,
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order_base_2(info->msi_count));
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if (ret) {
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dev_err(dev, "Failed to set MSI configuration: %d\n", ret);
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return ret;
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}
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ret = pci_epc_write_header(epc, epf->func_no, epf->vfunc_no,
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epf->header);
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if (ret) {
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dev_err(dev, "Failed to set Configuration header: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int pci_epf_mhi_link_up(struct pci_epf *epf)
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{
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struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf);
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const struct pci_epf_mhi_ep_info *info = epf_mhi->info;
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struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl;
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struct pci_epc *epc = epf->epc;
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struct device *dev = &epf->dev;
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int ret;
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mhi_cntrl->mmio = epf_mhi->mmio;
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mhi_cntrl->irq = epf_mhi->irq;
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mhi_cntrl->mru = info->mru;
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/* Assign the struct dev of PCI EP as MHI controller device */
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mhi_cntrl->cntrl_dev = epc->dev.parent;
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mhi_cntrl->raise_irq = pci_epf_mhi_raise_irq;
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mhi_cntrl->alloc_map = pci_epf_mhi_alloc_map;
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mhi_cntrl->unmap_free = pci_epf_mhi_unmap_free;
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mhi_cntrl->read_from_host = pci_epf_mhi_read_from_host;
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mhi_cntrl->write_to_host = pci_epf_mhi_write_to_host;
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/* Register the MHI EP controller */
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ret = mhi_ep_register_controller(mhi_cntrl, info->config);
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if (ret) {
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dev_err(dev, "Failed to register MHI EP controller: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int pci_epf_mhi_link_down(struct pci_epf *epf)
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{
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struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf);
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struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl;
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if (mhi_cntrl->mhi_dev) {
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mhi_ep_power_down(mhi_cntrl);
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mhi_ep_unregister_controller(mhi_cntrl);
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}
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return 0;
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}
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static int pci_epf_mhi_bme(struct pci_epf *epf)
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{
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struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf);
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struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl;
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struct device *dev = &epf->dev;
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int ret;
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/*
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* Power up the MHI EP stack if link is up and stack is in power down
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* state.
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*/
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if (!mhi_cntrl->enabled && mhi_cntrl->mhi_dev) {
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ret = mhi_ep_power_up(mhi_cntrl);
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if (ret) {
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dev_err(dev, "Failed to power up MHI EP: %d\n", ret);
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mhi_ep_unregister_controller(mhi_cntrl);
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}
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}
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return 0;
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}
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static int pci_epf_mhi_bind(struct pci_epf *epf)
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{
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struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf);
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struct pci_epc *epc = epf->epc;
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struct platform_device *pdev = to_platform_device(epc->dev.parent);
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struct resource *res;
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int ret;
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/* Get MMIO base address from Endpoint controller */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mmio");
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epf_mhi->mmio_phys = res->start;
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epf_mhi->mmio_size = resource_size(res);
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epf_mhi->mmio = ioremap(epf_mhi->mmio_phys, epf_mhi->mmio_size);
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if (!epf_mhi->mmio)
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return -ENOMEM;
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ret = platform_get_irq_byname(pdev, "doorbell");
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if (ret < 0) {
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iounmap(epf_mhi->mmio);
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return ret;
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}
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epf_mhi->irq = ret;
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return 0;
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}
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static void pci_epf_mhi_unbind(struct pci_epf *epf)
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{
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struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf);
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const struct pci_epf_mhi_ep_info *info = epf_mhi->info;
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struct pci_epf_bar *epf_bar = &epf->bar[info->bar_num];
|
||
|
struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl;
|
||
|
struct pci_epc *epc = epf->epc;
|
||
|
|
||
|
/*
|
||
|
* Forcefully power down the MHI EP stack. Only way to bring the MHI EP
|
||
|
* stack back to working state after successive bind is by getting BME
|
||
|
* from host.
|
||
|
*/
|
||
|
if (mhi_cntrl->mhi_dev) {
|
||
|
mhi_ep_power_down(mhi_cntrl);
|
||
|
mhi_ep_unregister_controller(mhi_cntrl);
|
||
|
}
|
||
|
|
||
|
iounmap(epf_mhi->mmio);
|
||
|
pci_epc_clear_bar(epc, epf->func_no, epf->vfunc_no, epf_bar);
|
||
|
}
|
||
|
|
||
|
static struct pci_epc_event_ops pci_epf_mhi_event_ops = {
|
||
|
.core_init = pci_epf_mhi_core_init,
|
||
|
.link_up = pci_epf_mhi_link_up,
|
||
|
.link_down = pci_epf_mhi_link_down,
|
||
|
.bme = pci_epf_mhi_bme,
|
||
|
};
|
||
|
|
||
|
static int pci_epf_mhi_probe(struct pci_epf *epf,
|
||
|
const struct pci_epf_device_id *id)
|
||
|
{
|
||
|
struct pci_epf_mhi_ep_info *info =
|
||
|
(struct pci_epf_mhi_ep_info *)id->driver_data;
|
||
|
struct pci_epf_mhi *epf_mhi;
|
||
|
struct device *dev = &epf->dev;
|
||
|
|
||
|
epf_mhi = devm_kzalloc(dev, sizeof(*epf_mhi), GFP_KERNEL);
|
||
|
if (!epf_mhi)
|
||
|
return -ENOMEM;
|
||
|
|
||
|
epf->header = info->epf_header;
|
||
|
epf_mhi->info = info;
|
||
|
epf_mhi->epf = epf;
|
||
|
|
||
|
epf->event_ops = &pci_epf_mhi_event_ops;
|
||
|
|
||
|
mutex_init(&epf_mhi->lock);
|
||
|
|
||
|
epf_set_drvdata(epf, epf_mhi);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static const struct pci_epf_device_id pci_epf_mhi_ids[] = {
|
||
|
{
|
||
|
.name = "sdx55", .driver_data = (kernel_ulong_t)&sdx55_info,
|
||
|
},
|
||
|
{},
|
||
|
};
|
||
|
|
||
|
static struct pci_epf_ops pci_epf_mhi_ops = {
|
||
|
.unbind = pci_epf_mhi_unbind,
|
||
|
.bind = pci_epf_mhi_bind,
|
||
|
};
|
||
|
|
||
|
static struct pci_epf_driver pci_epf_mhi_driver = {
|
||
|
.driver.name = "pci_epf_mhi",
|
||
|
.probe = pci_epf_mhi_probe,
|
||
|
.id_table = pci_epf_mhi_ids,
|
||
|
.ops = &pci_epf_mhi_ops,
|
||
|
.owner = THIS_MODULE,
|
||
|
};
|
||
|
|
||
|
static int __init pci_epf_mhi_init(void)
|
||
|
{
|
||
|
return pci_epf_register_driver(&pci_epf_mhi_driver);
|
||
|
}
|
||
|
module_init(pci_epf_mhi_init);
|
||
|
|
||
|
static void __exit pci_epf_mhi_exit(void)
|
||
|
{
|
||
|
pci_epf_unregister_driver(&pci_epf_mhi_driver);
|
||
|
}
|
||
|
module_exit(pci_epf_mhi_exit);
|
||
|
|
||
|
MODULE_DESCRIPTION("PCI EPF driver for MHI Endpoint devices");
|
||
|
MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
|
||
|
MODULE_LICENSE("GPL");
|