384 lines
9.7 KiB
C
384 lines
9.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* StarFive JH71XX PMU (Power Management Unit) Controller Driver
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*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <dt-bindings/power/starfive,jh7110-pmu.h>
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/* register offset */
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#define JH71XX_PMU_SW_TURN_ON_POWER 0x0C
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#define JH71XX_PMU_SW_TURN_OFF_POWER 0x10
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#define JH71XX_PMU_SW_ENCOURAGE 0x44
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#define JH71XX_PMU_TIMER_INT_MASK 0x48
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#define JH71XX_PMU_CURR_POWER_MODE 0x80
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#define JH71XX_PMU_EVENT_STATUS 0x88
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#define JH71XX_PMU_INT_STATUS 0x8C
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/* sw encourage cfg */
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#define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05
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#define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50
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#define JH71XX_PMU_SW_ENCOURAGE_DIS_LO 0x0A
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#define JH71XX_PMU_SW_ENCOURAGE_DIS_HI 0xA0
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#define JH71XX_PMU_SW_ENCOURAGE_ON 0xFF
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/* pmu int status */
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#define JH71XX_PMU_INT_SEQ_DONE BIT(0)
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#define JH71XX_PMU_INT_HW_REQ BIT(1)
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#define JH71XX_PMU_INT_SW_FAIL GENMASK(3, 2)
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#define JH71XX_PMU_INT_HW_FAIL GENMASK(5, 4)
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#define JH71XX_PMU_INT_PCH_FAIL GENMASK(8, 6)
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#define JH71XX_PMU_INT_ALL_MASK GENMASK(8, 0)
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/*
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* The time required for switching power status is based on the time
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* to turn on the largest domain's power, which is at microsecond level
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*/
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#define JH71XX_PMU_TIMEOUT_US 100
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struct jh71xx_domain_info {
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const char * const name;
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unsigned int flags;
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u8 bit;
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};
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struct jh71xx_pmu_match_data {
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const struct jh71xx_domain_info *domain_info;
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int num_domains;
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};
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struct jh71xx_pmu {
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struct device *dev;
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const struct jh71xx_pmu_match_data *match_data;
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void __iomem *base;
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struct generic_pm_domain **genpd;
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struct genpd_onecell_data genpd_data;
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int irq;
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spinlock_t lock; /* protects pmu reg */
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};
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struct jh71xx_pmu_dev {
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const struct jh71xx_domain_info *domain_info;
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struct jh71xx_pmu *pmu;
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struct generic_pm_domain genpd;
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};
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static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_on)
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{
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struct jh71xx_pmu *pmu = pmd->pmu;
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if (!mask)
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return -EINVAL;
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*is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask;
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return 0;
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}
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static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
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{
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struct jh71xx_pmu *pmu = pmd->pmu;
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unsigned long flags;
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u32 val;
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u32 mode;
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u32 encourage_lo;
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u32 encourage_hi;
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bool is_on;
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int ret;
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ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
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if (ret) {
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dev_dbg(pmu->dev, "unable to get current state for %s\n",
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pmd->genpd.name);
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return ret;
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}
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if (is_on == on) {
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dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
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pmd->genpd.name, on ? "en" : "dis");
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return 0;
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}
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spin_lock_irqsave(&pmu->lock, flags);
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/*
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* The PMU accepts software encourage to switch power mode in the following 2 steps:
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*
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* 1.Configure the register SW_TURN_ON_POWER (offset 0x0c) by writing 1 to
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* the bit corresponding to the power domain that will be turned on
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* and writing 0 to the others.
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* Likewise, configure the register SW_TURN_OFF_POWER (offset 0x10) by
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* writing 1 to the bit corresponding to the power domain that will be
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* turned off and writing 0 to the others.
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*/
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if (on) {
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mode = JH71XX_PMU_SW_TURN_ON_POWER;
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encourage_lo = JH71XX_PMU_SW_ENCOURAGE_EN_LO;
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encourage_hi = JH71XX_PMU_SW_ENCOURAGE_EN_HI;
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} else {
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mode = JH71XX_PMU_SW_TURN_OFF_POWER;
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encourage_lo = JH71XX_PMU_SW_ENCOURAGE_DIS_LO;
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encourage_hi = JH71XX_PMU_SW_ENCOURAGE_DIS_HI;
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}
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writel(mask, pmu->base + mode);
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/*
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* 2.Write SW encourage command sequence to the Software Encourage Reg (offset 0x44)
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* First write SW_MODE_ENCOURAGE_ON to JH71XX_PMU_SW_ENCOURAGE. This will reset
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* the state machine which parses the command sequence. This register must be
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* written every time software wants to power on/off a domain.
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* Then write the lower bits of the command sequence, followed by the upper
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* bits. The sequence differs between powering on & off a domain.
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*/
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writel(JH71XX_PMU_SW_ENCOURAGE_ON, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
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writel(encourage_lo, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
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writel(encourage_hi, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
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spin_unlock_irqrestore(&pmu->lock, flags);
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/* Wait for the power domain bit to be enabled / disabled */
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if (on) {
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ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE,
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val, val & mask,
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1, JH71XX_PMU_TIMEOUT_US);
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} else {
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ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE,
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val, !(val & mask),
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1, JH71XX_PMU_TIMEOUT_US);
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}
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if (ret) {
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dev_err(pmu->dev, "%s: failed to power %s\n",
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pmd->genpd.name, on ? "on" : "off");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int jh71xx_pmu_on(struct generic_pm_domain *genpd)
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{
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struct jh71xx_pmu_dev *pmd = container_of(genpd,
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struct jh71xx_pmu_dev, genpd);
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u32 pwr_mask = BIT(pmd->domain_info->bit);
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return jh71xx_pmu_set_state(pmd, pwr_mask, true);
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}
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static int jh71xx_pmu_off(struct generic_pm_domain *genpd)
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{
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struct jh71xx_pmu_dev *pmd = container_of(genpd,
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struct jh71xx_pmu_dev, genpd);
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u32 pwr_mask = BIT(pmd->domain_info->bit);
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return jh71xx_pmu_set_state(pmd, pwr_mask, false);
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}
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static void jh71xx_pmu_int_enable(struct jh71xx_pmu *pmu, u32 mask, bool enable)
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{
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u32 val;
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unsigned long flags;
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spin_lock_irqsave(&pmu->lock, flags);
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val = readl(pmu->base + JH71XX_PMU_TIMER_INT_MASK);
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if (enable)
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val &= ~mask;
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else
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val |= mask;
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writel(val, pmu->base + JH71XX_PMU_TIMER_INT_MASK);
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spin_unlock_irqrestore(&pmu->lock, flags);
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}
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static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data)
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{
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struct jh71xx_pmu *pmu = data;
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u32 val;
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val = readl(pmu->base + JH71XX_PMU_INT_STATUS);
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if (val & JH71XX_PMU_INT_SEQ_DONE)
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dev_dbg(pmu->dev, "sequence done.\n");
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if (val & JH71XX_PMU_INT_HW_REQ)
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dev_dbg(pmu->dev, "hardware encourage requestion.\n");
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if (val & JH71XX_PMU_INT_SW_FAIL)
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dev_err(pmu->dev, "software encourage fail.\n");
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if (val & JH71XX_PMU_INT_HW_FAIL)
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dev_err(pmu->dev, "hardware encourage fail.\n");
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if (val & JH71XX_PMU_INT_PCH_FAIL)
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dev_err(pmu->dev, "p-channel fail event.\n");
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/* clear interrupts */
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writel(val, pmu->base + JH71XX_PMU_INT_STATUS);
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writel(val, pmu->base + JH71XX_PMU_EVENT_STATUS);
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return IRQ_HANDLED;
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}
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static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index)
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{
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struct jh71xx_pmu_dev *pmd;
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u32 pwr_mask;
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int ret;
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bool is_on = false;
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pmd = devm_kzalloc(pmu->dev, sizeof(*pmd), GFP_KERNEL);
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if (!pmd)
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return -ENOMEM;
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pmd->domain_info = &pmu->match_data->domain_info[index];
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pmd->pmu = pmu;
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pwr_mask = BIT(pmd->domain_info->bit);
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pmd->genpd.name = pmd->domain_info->name;
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pmd->genpd.flags = pmd->domain_info->flags;
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ret = jh71xx_pmu_get_state(pmd, pwr_mask, &is_on);
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if (ret)
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dev_warn(pmu->dev, "unable to get current state for %s\n",
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pmd->genpd.name);
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pmd->genpd.power_on = jh71xx_pmu_on;
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pmd->genpd.power_off = jh71xx_pmu_off;
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pm_genpd_init(&pmd->genpd, NULL, !is_on);
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pmu->genpd_data.domains[index] = &pmd->genpd;
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return 0;
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}
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static int jh71xx_pmu_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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const struct jh71xx_pmu_match_data *match_data;
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struct jh71xx_pmu *pmu;
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unsigned int i;
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int ret;
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pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL);
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if (!pmu)
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return -ENOMEM;
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pmu->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pmu->base))
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return PTR_ERR(pmu->base);
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pmu->irq = platform_get_irq(pdev, 0);
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if (pmu->irq < 0)
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return pmu->irq;
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ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
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0, pdev->name, pmu);
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if (ret)
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dev_err(dev, "failed to request irq\n");
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match_data = of_device_get_match_data(dev);
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if (!match_data)
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return -EINVAL;
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pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
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sizeof(struct generic_pm_domain *),
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GFP_KERNEL);
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if (!pmu->genpd)
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return -ENOMEM;
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pmu->dev = dev;
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pmu->match_data = match_data;
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pmu->genpd_data.domains = pmu->genpd;
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pmu->genpd_data.num_domains = match_data->num_domains;
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for (i = 0; i < match_data->num_domains; i++) {
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ret = jh71xx_pmu_init_domain(pmu, i);
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if (ret) {
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dev_err(dev, "failed to initialize power domain\n");
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return ret;
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}
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}
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spin_lock_init(&pmu->lock);
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jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
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ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
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if (ret) {
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dev_err(dev, "failed to register genpd driver: %d\n", ret);
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return ret;
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}
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dev_dbg(dev, "registered %u power domains\n", i);
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return 0;
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}
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static const struct jh71xx_domain_info jh7110_power_domains[] = {
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[JH7110_PD_SYSTOP] = {
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.name = "SYSTOP",
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.bit = 0,
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.flags = GENPD_FLAG_ALWAYS_ON,
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},
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[JH7110_PD_CPU] = {
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.name = "CPU",
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.bit = 1,
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.flags = GENPD_FLAG_ALWAYS_ON,
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},
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[JH7110_PD_GPUA] = {
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.name = "GPUA",
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.bit = 2,
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},
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[JH7110_PD_VDEC] = {
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.name = "VDEC",
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.bit = 3,
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},
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[JH7110_PD_VOUT] = {
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.name = "VOUT",
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.bit = 4,
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|
},
|
||
|
|
[JH7110_PD_ISP] = {
|
||
|
|
.name = "ISP",
|
||
|
|
.bit = 5,
|
||
|
|
},
|
||
|
|
[JH7110_PD_VENC] = {
|
||
|
|
.name = "VENC",
|
||
|
|
.bit = 6,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct jh71xx_pmu_match_data jh7110_pmu = {
|
||
|
|
.num_domains = ARRAY_SIZE(jh7110_power_domains),
|
||
|
|
.domain_info = jh7110_power_domains,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id jh71xx_pmu_of_match[] = {
|
||
|
|
{
|
||
|
|
.compatible = "starfive,jh7110-pmu",
|
||
|
|
.data = (void *)&jh7110_pmu,
|
||
|
|
}, {
|
||
|
|
/* sentinel */
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_driver jh71xx_pmu_driver = {
|
||
|
|
.probe = jh71xx_pmu_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "jh71xx-pmu",
|
||
|
|
.of_match_table = jh71xx_pmu_of_match,
|
||
|
|
.suppress_bind_attrs = true,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
builtin_platform_driver(jh71xx_pmu_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Walker Chen <walker.chen@starfivetech.com>");
|
||
|
|
MODULE_DESCRIPTION("StarFive JH71XX PMU Driver");
|
||
|
|
MODULE_LICENSE("GPL");
|