187 lines
5.1 KiB
C
187 lines
5.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MT8135_H
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#define _DT_BINDINGS_CLK_MT8135_H
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/* TOPCKGEN */
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#define CLK_TOP_DSI0_LNTC_DSICLK 1
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#define CLK_TOP_HDMITX_CLKDIG_CTS 2
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#define CLK_TOP_CLKPH_MCK 3
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#define CLK_TOP_CPUM_TCK_IN 4
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#define CLK_TOP_MAINPLL_806M 5
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#define CLK_TOP_MAINPLL_537P3M 6
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#define CLK_TOP_MAINPLL_322P4M 7
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#define CLK_TOP_MAINPLL_230P3M 8
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#define CLK_TOP_UNIVPLL_624M 9
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#define CLK_TOP_UNIVPLL_416M 10
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#define CLK_TOP_UNIVPLL_249P6M 11
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#define CLK_TOP_UNIVPLL_178P3M 12
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#define CLK_TOP_UNIVPLL_48M 13
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#define CLK_TOP_MMPLL_D2 14
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#define CLK_TOP_MMPLL_D3 15
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#define CLK_TOP_MMPLL_D5 16
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#define CLK_TOP_MMPLL_D7 17
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#define CLK_TOP_MMPLL_D4 18
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#define CLK_TOP_MMPLL_D6 19
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#define CLK_TOP_SYSPLL_D2 20
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#define CLK_TOP_SYSPLL_D4 21
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#define CLK_TOP_SYSPLL_D6 22
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#define CLK_TOP_SYSPLL_D8 23
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#define CLK_TOP_SYSPLL_D10 24
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#define CLK_TOP_SYSPLL_D12 25
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#define CLK_TOP_SYSPLL_D16 26
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#define CLK_TOP_SYSPLL_D24 27
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#define CLK_TOP_SYSPLL_D3 28
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#define CLK_TOP_SYSPLL_D2P5 29
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#define CLK_TOP_SYSPLL_D5 30
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#define CLK_TOP_SYSPLL_D3P5 31
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#define CLK_TOP_UNIVPLL1_D2 32
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#define CLK_TOP_UNIVPLL1_D4 33
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#define CLK_TOP_UNIVPLL1_D6 34
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#define CLK_TOP_UNIVPLL1_D8 35
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#define CLK_TOP_UNIVPLL1_D10 36
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#define CLK_TOP_UNIVPLL2_D2 37
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#define CLK_TOP_UNIVPLL2_D4 38
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#define CLK_TOP_UNIVPLL2_D6 39
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#define CLK_TOP_UNIVPLL2_D8 40
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#define CLK_TOP_UNIVPLL_D3 41
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#define CLK_TOP_UNIVPLL_D5 42
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#define CLK_TOP_UNIVPLL_D7 43
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#define CLK_TOP_UNIVPLL_D10 44
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#define CLK_TOP_UNIVPLL_D26 45
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#define CLK_TOP_APLL 46
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#define CLK_TOP_APLL_D4 47
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#define CLK_TOP_APLL_D8 48
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#define CLK_TOP_APLL_D16 49
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#define CLK_TOP_APLL_D24 50
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#define CLK_TOP_LVDSPLL_D2 51
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#define CLK_TOP_LVDSPLL_D4 52
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#define CLK_TOP_LVDSPLL_D8 53
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#define CLK_TOP_LVDSTX_CLKDIG_CT 54
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#define CLK_TOP_VPLL_DPIX 55
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#define CLK_TOP_TVHDMI_H 56
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#define CLK_TOP_HDMITX_CLKDIG_D2 57
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#define CLK_TOP_HDMITX_CLKDIG_D3 58
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#define CLK_TOP_TVHDMI_D2 59
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#define CLK_TOP_TVHDMI_D4 60
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#define CLK_TOP_MEMPLL_MCK_D4 61
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#define CLK_TOP_AXI_SEL 62
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#define CLK_TOP_SMI_SEL 63
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#define CLK_TOP_MFG_SEL 64
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#define CLK_TOP_IRDA_SEL 65
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#define CLK_TOP_CAM_SEL 66
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#define CLK_TOP_AUD_INTBUS_SEL 67
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#define CLK_TOP_JPG_SEL 68
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#define CLK_TOP_DISP_SEL 69
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#define CLK_TOP_MSDC30_1_SEL 70
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#define CLK_TOP_MSDC30_2_SEL 71
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#define CLK_TOP_MSDC30_3_SEL 72
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#define CLK_TOP_MSDC30_4_SEL 73
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#define CLK_TOP_USB20_SEL 74
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#define CLK_TOP_VENC_SEL 75
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#define CLK_TOP_SPI_SEL 76
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#define CLK_TOP_UART_SEL 77
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#define CLK_TOP_MEM_SEL 78
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#define CLK_TOP_CAMTG_SEL 79
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#define CLK_TOP_AUDIO_SEL 80
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#define CLK_TOP_FIX_SEL 81
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#define CLK_TOP_VDEC_SEL 82
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#define CLK_TOP_DDRPHYCFG_SEL 83
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#define CLK_TOP_DPILVDS_SEL 84
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#define CLK_TOP_PMICSPI_SEL 85
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#define CLK_TOP_MSDC30_0_SEL 86
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#define CLK_TOP_SMI_MFG_AS_SEL 87
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#define CLK_TOP_GCPU_SEL 88
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#define CLK_TOP_DPI1_SEL 89
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#define CLK_TOP_CCI_SEL 90
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#define CLK_TOP_APLL_SEL 91
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#define CLK_TOP_HDMIPLL_SEL 92
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#define CLK_TOP_NR_CLK 93
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/* APMIXED_SYS */
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#define CLK_APMIXED_ARMPLL1 1
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#define CLK_APMIXED_ARMPLL2 2
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#define CLK_APMIXED_MAINPLL 3
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#define CLK_APMIXED_UNIVPLL 4
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#define CLK_APMIXED_MMPLL 5
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#define CLK_APMIXED_MSDCPLL 6
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#define CLK_APMIXED_TVDPLL 7
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#define CLK_APMIXED_LVDSPLL 8
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#define CLK_APMIXED_AUDPLL 9
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#define CLK_APMIXED_VDECPLL 10
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#define CLK_APMIXED_NR_CLK 11
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/* INFRA_SYS */
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#define CLK_INFRA_PMIC_WRAP 1
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#define CLK_INFRA_PMICSPI 2
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#define CLK_INFRA_CCIF1_AP_CTRL 3
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#define CLK_INFRA_CCIF0_AP_CTRL 4
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#define CLK_INFRA_KP 5
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#define CLK_INFRA_CPUM 6
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#define CLK_INFRA_M4U 7
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#define CLK_INFRA_MFGAXI 8
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#define CLK_INFRA_DEVAPC 9
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#define CLK_INFRA_AUDIO 10
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#define CLK_INFRA_MFG_BUS 11
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#define CLK_INFRA_SMI 12
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#define CLK_INFRA_DBGCLK 13
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#define CLK_INFRA_NR_CLK 14
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/* PERI_SYS */
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#define CLK_PERI_I2C5 1
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#define CLK_PERI_I2C4 2
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#define CLK_PERI_I2C3 3
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#define CLK_PERI_I2C2 4
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#define CLK_PERI_I2C1 5
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#define CLK_PERI_I2C0 6
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#define CLK_PERI_UART3 7
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#define CLK_PERI_UART2 8
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#define CLK_PERI_UART1 9
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#define CLK_PERI_UART0 10
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#define CLK_PERI_IRDA 11
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#define CLK_PERI_NLI 12
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#define CLK_PERI_MD_HIF 13
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#define CLK_PERI_AP_HIF 14
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#define CLK_PERI_MSDC30_3 15
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#define CLK_PERI_MSDC30_2 16
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#define CLK_PERI_MSDC30_1 17
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#define CLK_PERI_MSDC20_2 18
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#define CLK_PERI_MSDC20_1 19
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#define CLK_PERI_AP_DMA 20
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#define CLK_PERI_USB1 21
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#define CLK_PERI_USB0 22
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#define CLK_PERI_PWM 23
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#define CLK_PERI_PWM7 24
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#define CLK_PERI_PWM6 25
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#define CLK_PERI_PWM5 26
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#define CLK_PERI_PWM4 27
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#define CLK_PERI_PWM3 28
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#define CLK_PERI_PWM2 29
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#define CLK_PERI_PWM1 30
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#define CLK_PERI_THERM 31
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#define CLK_PERI_NFI 32
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#define CLK_PERI_USBSLV 33
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#define CLK_PERI_USB1_MCU 34
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#define CLK_PERI_USB0_MCU 35
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#define CLK_PERI_GCPU 36
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#define CLK_PERI_FHCTL 37
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#define CLK_PERI_SPI1 38
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#define CLK_PERI_AUXADC 39
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#define CLK_PERI_PERI_PWRAP 40
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#define CLK_PERI_I2C6 41
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#define CLK_PERI_UART0_SEL 42
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#define CLK_PERI_UART1_SEL 43
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#define CLK_PERI_UART2_SEL 44
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#define CLK_PERI_UART3_SEL 45
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#define CLK_PERI_NR_CLK 46
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#endif /* _DT_BINDINGS_CLK_MT8135_H */
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