112 lines
3.2 KiB
C
112 lines
3.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA30_MC_H
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#define TEGRA_SWGROUP_PTC 0
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#define TEGRA_SWGROUP_DC 1
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#define TEGRA_SWGROUP_DCB 2
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#define TEGRA_SWGROUP_EPP 3
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#define TEGRA_SWGROUP_G2 4
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#define TEGRA_SWGROUP_MPE 5
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#define TEGRA_SWGROUP_VI 6
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#define TEGRA_SWGROUP_AFI 7
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#define TEGRA_SWGROUP_AVPC 8
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#define TEGRA_SWGROUP_NV 9
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#define TEGRA_SWGROUP_NV2 10
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#define TEGRA_SWGROUP_HDA 11
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#define TEGRA_SWGROUP_HC 12
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#define TEGRA_SWGROUP_PPCS 13
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#define TEGRA_SWGROUP_SATA 14
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#define TEGRA_SWGROUP_VDE 15
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#define TEGRA_SWGROUP_MPCORELP 16
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#define TEGRA_SWGROUP_MPCORE 17
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#define TEGRA_SWGROUP_ISP 18
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#define TEGRA30_MC_RESET_AFI 0
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#define TEGRA30_MC_RESET_AVPC 1
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#define TEGRA30_MC_RESET_DC 2
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#define TEGRA30_MC_RESET_DCB 3
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#define TEGRA30_MC_RESET_EPP 4
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#define TEGRA30_MC_RESET_2D 5
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#define TEGRA30_MC_RESET_HC 6
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#define TEGRA30_MC_RESET_HDA 7
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#define TEGRA30_MC_RESET_ISP 8
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#define TEGRA30_MC_RESET_MPCORE 9
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#define TEGRA30_MC_RESET_MPCORELP 10
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#define TEGRA30_MC_RESET_MPE 11
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#define TEGRA30_MC_RESET_3D 12
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#define TEGRA30_MC_RESET_3D2 13
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#define TEGRA30_MC_RESET_PPCS 14
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#define TEGRA30_MC_RESET_SATA 15
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#define TEGRA30_MC_RESET_VDE 16
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#define TEGRA30_MC_RESET_VI 17
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#define TEGRA30_MC_PTCR 0
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#define TEGRA30_MC_DISPLAY0A 1
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#define TEGRA30_MC_DISPLAY0AB 2
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#define TEGRA30_MC_DISPLAY0B 3
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#define TEGRA30_MC_DISPLAY0BB 4
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#define TEGRA30_MC_DISPLAY0C 5
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#define TEGRA30_MC_DISPLAY0CB 6
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#define TEGRA30_MC_DISPLAY1B 7
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#define TEGRA30_MC_DISPLAY1BB 8
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#define TEGRA30_MC_EPPUP 9
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#define TEGRA30_MC_G2PR 10
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#define TEGRA30_MC_G2SR 11
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#define TEGRA30_MC_MPEUNIFBR 12
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#define TEGRA30_MC_VIRUV 13
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#define TEGRA30_MC_AFIR 14
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#define TEGRA30_MC_AVPCARM7R 15
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#define TEGRA30_MC_DISPLAYHC 16
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#define TEGRA30_MC_DISPLAYHCB 17
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#define TEGRA30_MC_FDCDRD 18
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#define TEGRA30_MC_FDCDRD2 19
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#define TEGRA30_MC_G2DR 20
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#define TEGRA30_MC_HDAR 21
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#define TEGRA30_MC_HOST1XDMAR 22
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#define TEGRA30_MC_HOST1XR 23
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#define TEGRA30_MC_IDXSRD 24
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#define TEGRA30_MC_IDXSRD2 25
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#define TEGRA30_MC_MPE_IPRED 26
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#define TEGRA30_MC_MPEAMEMRD 27
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#define TEGRA30_MC_MPECSRD 28
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#define TEGRA30_MC_PPCSAHBDMAR 29
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#define TEGRA30_MC_PPCSAHBSLVR 30
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#define TEGRA30_MC_SATAR 31
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#define TEGRA30_MC_TEXSRD 32
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#define TEGRA30_MC_TEXSRD2 33
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#define TEGRA30_MC_VDEBSEVR 34
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#define TEGRA30_MC_VDEMBER 35
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#define TEGRA30_MC_VDEMCER 36
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#define TEGRA30_MC_VDETPER 37
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#define TEGRA30_MC_MPCORELPR 38
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#define TEGRA30_MC_MPCORER 39
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#define TEGRA30_MC_EPPU 40
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#define TEGRA30_MC_EPPV 41
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#define TEGRA30_MC_EPPY 42
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#define TEGRA30_MC_MPEUNIFBW 43
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#define TEGRA30_MC_VIWSB 44
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#define TEGRA30_MC_VIWU 45
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#define TEGRA30_MC_VIWV 46
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#define TEGRA30_MC_VIWY 47
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#define TEGRA30_MC_G2DW 48
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#define TEGRA30_MC_AFIW 49
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#define TEGRA30_MC_AVPCARM7W 50
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#define TEGRA30_MC_FDCDWR 51
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#define TEGRA30_MC_FDCDWR2 52
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#define TEGRA30_MC_HDAW 53
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#define TEGRA30_MC_HOST1XW 54
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#define TEGRA30_MC_ISPW 55
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#define TEGRA30_MC_MPCORELPW 56
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#define TEGRA30_MC_MPCOREW 57
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#define TEGRA30_MC_MPECSWR 58
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#define TEGRA30_MC_PPCSAHBDMAW 59
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#define TEGRA30_MC_PPCSAHBSLVW 60
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#define TEGRA30_MC_SATAW 61
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#define TEGRA30_MC_VDEBSEVW 62
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#define TEGRA30_MC_VDEDBGW 63
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#define TEGRA30_MC_VDEMBEW 64
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#define TEGRA30_MC_VDETPMW 65
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#endif
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