109 lines
3.0 KiB
C
109 lines
3.0 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2023 Nuvoton Technologies.
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* Author: Chi-Fen Li <cfli0@nuvoton.com>
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*
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* Device Tree binding constants for MA35D1 reset controller.
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*/
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#ifndef __DT_BINDINGS_RESET_MA35D1_H
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#define __DT_BINDINGS_RESET_MA35D1_H
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#define MA35D1_RESET_CHIP 0
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#define MA35D1_RESET_CA35CR0 1
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#define MA35D1_RESET_CA35CR1 2
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#define MA35D1_RESET_CM4 3
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#define MA35D1_RESET_PDMA0 4
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#define MA35D1_RESET_PDMA1 5
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#define MA35D1_RESET_PDMA2 6
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#define MA35D1_RESET_PDMA3 7
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#define MA35D1_RESET_DISP 8
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#define MA35D1_RESET_VCAP0 9
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#define MA35D1_RESET_VCAP1 10
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#define MA35D1_RESET_GFX 11
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#define MA35D1_RESET_VDEC 12
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#define MA35D1_RESET_WHC0 13
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#define MA35D1_RESET_WHC1 14
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#define MA35D1_RESET_GMAC0 15
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#define MA35D1_RESET_GMAC1 16
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#define MA35D1_RESET_HWSEM 17
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#define MA35D1_RESET_EBI 18
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#define MA35D1_RESET_HSUSBH0 19
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#define MA35D1_RESET_HSUSBH1 20
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#define MA35D1_RESET_HSUSBD 21
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#define MA35D1_RESET_USBHL 22
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#define MA35D1_RESET_SDH0 23
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#define MA35D1_RESET_SDH1 24
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#define MA35D1_RESET_NAND 25
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#define MA35D1_RESET_GPIO 26
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#define MA35D1_RESET_MCTLP 27
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#define MA35D1_RESET_MCTLC 28
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#define MA35D1_RESET_DDRPUB 29
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#define MA35D1_RESET_TMR0 30
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#define MA35D1_RESET_TMR1 31
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#define MA35D1_RESET_TMR2 32
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#define MA35D1_RESET_TMR3 33
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#define MA35D1_RESET_I2C0 34
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#define MA35D1_RESET_I2C1 35
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#define MA35D1_RESET_I2C2 36
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#define MA35D1_RESET_I2C3 37
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#define MA35D1_RESET_QSPI0 38
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#define MA35D1_RESET_SPI0 39
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#define MA35D1_RESET_SPI1 40
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#define MA35D1_RESET_SPI2 41
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#define MA35D1_RESET_UART0 42
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#define MA35D1_RESET_UART1 43
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#define MA35D1_RESET_UART2 44
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#define MA35D1_RESET_UART3 45
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#define MA35D1_RESET_UART4 46
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#define MA35D1_RESET_UART5 47
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#define MA35D1_RESET_UART6 48
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#define MA35D1_RESET_UART7 49
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#define MA35D1_RESET_CANFD0 50
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#define MA35D1_RESET_CANFD1 51
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#define MA35D1_RESET_EADC0 52
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#define MA35D1_RESET_I2S0 53
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#define MA35D1_RESET_SC0 54
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#define MA35D1_RESET_SC1 55
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#define MA35D1_RESET_QSPI1 56
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#define MA35D1_RESET_SPI3 57
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#define MA35D1_RESET_EPWM0 58
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#define MA35D1_RESET_EPWM1 59
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#define MA35D1_RESET_QEI0 60
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#define MA35D1_RESET_QEI1 61
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#define MA35D1_RESET_ECAP0 62
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#define MA35D1_RESET_ECAP1 63
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#define MA35D1_RESET_CANFD2 64
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#define MA35D1_RESET_ADC0 65
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#define MA35D1_RESET_TMR4 66
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#define MA35D1_RESET_TMR5 67
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#define MA35D1_RESET_TMR6 68
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#define MA35D1_RESET_TMR7 69
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#define MA35D1_RESET_TMR8 70
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#define MA35D1_RESET_TMR9 71
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#define MA35D1_RESET_TMR10 72
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#define MA35D1_RESET_TMR11 73
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#define MA35D1_RESET_UART8 74
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#define MA35D1_RESET_UART9 75
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#define MA35D1_RESET_UART10 76
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#define MA35D1_RESET_UART11 77
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#define MA35D1_RESET_UART12 78
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#define MA35D1_RESET_UART13 79
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#define MA35D1_RESET_UART14 80
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#define MA35D1_RESET_UART15 81
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#define MA35D1_RESET_UART16 82
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#define MA35D1_RESET_I2S1 83
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#define MA35D1_RESET_I2C4 84
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#define MA35D1_RESET_I2C5 85
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#define MA35D1_RESET_EPWM2 86
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#define MA35D1_RESET_ECAP2 87
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#define MA35D1_RESET_QEI2 88
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#define MA35D1_RESET_CANFD3 89
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#define MA35D1_RESET_KPI 90
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#define MA35D1_RESET_GIC 91
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#define MA35D1_RESET_SSMCC 92
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#define MA35D1_RESET_SSPCC 93
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#define MA35D1_RESET_COUNT 94
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#endif
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