2023-08-30 17:31:07 +02:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* CCI cache coherent interconnect support
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*
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* Copyright (C) 2013 ARM Ltd.
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*/
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#ifndef __LINUX_ARM_CCI_H
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#define __LINUX_ARM_CCI_H
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <asm/arm-cci.h>
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struct device_node;
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#ifdef CONFIG_ARM_CCI
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extern bool cci_probed(void);
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#else
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static inline bool cci_probed(void) { return false; }
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#endif
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#ifdef CONFIG_ARM_CCI400_PORT_CTRL
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extern int cci_ace_get_port(struct device_node *dn);
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extern int cci_disable_port_by_cpu(u64 mpidr);
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extern int __cci_control_port_by_device(struct device_node *dn, bool enable);
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extern int __cci_control_port_by_index(u32 port, bool enable);
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#else
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static inline int cci_ace_get_port(struct device_node *dn)
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{
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return -ENODEV;
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}
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static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; }
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static inline int __cci_control_port_by_device(struct device_node *dn,
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bool enable)
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{
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return -ENODEV;
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}
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static inline int __cci_control_port_by_index(u32 port, bool enable)
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{
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return -ENODEV;
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}
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#endif
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2023-10-24 12:59:35 +02:00
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void cci_enable_port_for_self(void);
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2023-08-30 17:31:07 +02:00
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#define cci_disable_port_by_device(dev) \
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__cci_control_port_by_device(dev, false)
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#define cci_enable_port_by_device(dev) \
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__cci_control_port_by_device(dev, true)
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#define cci_disable_port_by_index(dev) \
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__cci_control_port_by_index(dev, false)
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#define cci_enable_port_by_index(dev) \
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__cci_control_port_by_index(dev, true)
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#endif
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